Refer to the PDF data sheet for device specific package drawings
The TPS65150 device offers a very compact and small power supply solution that provides all three voltages required by thin film transistor (TFT) LCD displays. With an input voltage range of 1.8 V to 6 V the device is ideal for notebooks powered by a 2.5-V or 3.3-V input rail or monitor applications with a 5-V input voltage rail. Additionally the TPS65150 device provides an integrated high current buffer to provide the VCOM voltage for the TFT backplane.
Two regulated adjustable charge pump driver provide the positive V(VGH) and negative V(VGL) bias voltages for the TFT. The device incorporates adjustable power-on sequencing for V(VGL) as well as for V(VGH). This avoids any additional external components to implement application specific sequencing. The device has an integrated high-voltage switch to isolate V(VGH).
The same internal circuit can also be used to provide a gate shaping signal of V(VGH) for the LCD panel controlled by the signal applied to the CTRL input. For highest safety, the TPS65150 device has an integrated adjustable shutdown latch feature, which allows application-specific flexibility. The device monitors the outputs (V(VS), V(VGL), V(VGH)); and, as soon as one of the outputs falls below its power good threshold, the device enters shutdown latch, after its adjustable delay time has passed by.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS65150 | HTSSOP (24) | 7.80 mm × 4.40 mm |
VQFN (24) | 4.00 mm × 4.00 mm |
Changes from A Revision (March 2015) to B Revision
Changes from * Revision (September 2005) to A Revision
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | VQFN | HTSSOP | ||
ADJ | 17 | 14 | I/O | Gate voltage shaping circuit. Connecting a capacitor to this pin sets the fall time of the positive gate voltage V(VGH). |
COMP | 1 | 22 | O | This is the compensation pin for the main boost converter. A small capacitor and if required a series resistor is connected to this pin. |
CPI | 19 | 16 | I | Input of the VGH isolation switch and gate voltage shaping circuit. |
CTRL | 16 | 13 | I | Control signal for the gate voltage shaping signal. Apply the control signal for the gate voltage control. Usually the timing controller of the LCD panel generates this signal. If this function is not required, this pin must be connected to VI. By doing this, the internal switch between CPI and VGH provides isolation for the positive charge pump output V(VGH). DLY2 sets the delay time for V(VGH) to come up. |
DLY1 | 5 | 2 | I/O | Power-on sequencing adjust. Connecting a capacitor from this pin to ground allows to set the delay time between the boost converter output V(VS) and the negative charge pump V(VGL) during start-up. |
DLY2 | 6 | 3 | I/O | Power-on sequencing adjust. Connecting a capacitor from this pin to ground allows to set the delay time between the negative charge pump V(VGL) and the positive charge pump during start-up. Note that Q5 in the gate voltage shaping block only turns on when the positive charge pump is within regulation. (This provides input-output isolation of V(VGH)). |
DRVN | 21 | 18 | I/O | Negative charge pump driver. |
DRVP | 20 | 17 | I/O | Positive charge pump driver. |
FB | 4 | 1 | I | Boost converter feedback sense input. |
FBN | 24 | 21 | I | Negative charge pump feedback sense input. |
FBP | 15 | 12 | I | Positive charge pump feedback sense input. |
FDLY | 3 | 24 | I/O | Fault delay. Connecting a capacitor from this pin to VI sets the delay time from the point when one or more of the of the outputs V(VS), V(VGH), V(VGL) drops below its power good threshold until the device shuts down. To restart the device, the input voltage must be cycled to ground. This feature can be disabled by connecting the FDLY pin to VI. |
GD | 2 | 23 | I | Active-low, open-drain output. This output is latched low when the boost converter output is in regulation. This signal can be used to drive an external MOSFET to provide isolation for V(VS). |
GND | 22 | 19 | Analog ground. | |
IN | 14 | 11 | I | Input of the VCOM buffer. If this pin is connected to ground, the VCOM buffer is disabled. |
PGND | 10, 11 | 7, 8 | Power ground. | |
REF | 23 | 20 | O | Internal reference output, typically 1.213 V. |
SUP | 12 | 9 | I/O | Supply pin of the positive, negative charge pump and boost converter gate drive circuit. This pin should be connected to the output of the main boost converter. |
SW | 8, 9 | 5, 6 | I | Switch pin of the boost converter. |
VCOM | 13 | 10 | O | VCOM buffer output. Typically a 1-µF output capacitor is required on this pin. |
VGH | 18 | 15 | O | Positive output voltage to drive the TFT gates with an adjustable fall time. This pin is internally connected with a MOSFET switch to the positive charge pump input CPI. |
VIN | 7 | 4 | I | This is the input voltage pin of the device. |
Thermal Pad | — | — | The thermal pad must to be soldered to GND |