TPS742 1.5A Ultra-LDO With Programmable Soft-Start
- SBVS064P December 2005 – February 2025 TPS74201
  
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Data Sheet

TPS742 1.5A Ultra-LDO With Programmable Soft-Start

1 Features

Input voltage range: 0.8V to 5.5V
Soft-start (SS) pin provides a linear start-up with ramp time set by external capacitor
1% accuracy over line, load, and temperature
Supports input voltages as low as 0.8V with external bias supply
Adjustable output (0.8V to 3.6V)
Ultra-Low Dropout:
- 60mV (legacy chip) at 1.5A (typical)
- 55mV (new chip) at 1.5A (typical)
Stable with any output capacitor ≥ 2.2μF (new chip)
Stable with any or no output capacitor (legacy chip)
Excellent transient response
Open-drain power-good
Active high enable

2 Applications

3 Description

The TPS742 series of low-dropout (LDO) linear regulators provide an easy-to-use, robust power-management solution for a wide variety of applications. User-programmable soft-start minimizes stress on the input power source by reducing capacitive inrush current on start-up. The soft-start is monotonic and well suited for powering many different types of processors and ASICs. The enable input and power-good output allow easy sequencing with external regulators. This complete flexibility permits the user to configure a solution that meets the sequencing requirements of FPGAs, DSPs, and other applications with special start-up requirements.

A precision reference and error amplifier deliver 1% accuracy over load, line, temperature, and process. The device is is stable with any type of capacitor greater than or equal to 2.2μF (new chip), and is fully specified from –40°C to 125°C.

Package Information

PART NUMBER	PACKAGE⁽¹⁾	PACKAGE SIZE⁽²⁾
TPS74201	RGW (VQFN, 20)	5mm × 5mm
	RGR (VQFN, 20)	3.5mm × 3.5mm
	KTW (DDPAK/TO-263, 7)	10.1mm × 15.24mm

(1) For all available packages, see the Mechanical, Packaging, and Orderable Information.

(2) The package size (length × width) is a nominal value and includes pins, where applicable.

Typical Application Adjustable Output Version

Turn-On Response

4 Pin Configuration and Functions

TPS74201 RGW and RGR Packages,20-Pin VQFN With Exposed Thermal Pad(Top View)

Figure 4-1 RGW and RGR Packages,20-Pin VQFN With Exposed Thermal Pad(Top View)

TPS74201 KTW Package,7-Pin DDPAK/TO-263(Top View, Legacy
Chip)

Figure 4-2 KTW Package,7-Pin DDPAK/TO-263(Top View, Legacy Chip)

Table 4-1 Pin Functions

PIN			TYPE⁽¹⁾	DESCRIPTION
NAME	KTW⁽²⁾ (DDPAK/ TO-263)	RGW, RGR⁽²⁾ (VQFN)	TYPE⁽¹⁾	DESCRIPTION
BIAS	6	10	I	Bias input voltage for error amplifier, reference, and internal control circuits.
EN	7	11	I	Enable pin. Driving this pin high enables the regulator. Driving this pin low puts the regulator into shutdown mode. This pin must not be left floating.
FB	2	16	I	This pin is the feedback connection to the center tap of an external resistor divider network that sets the output voltage. This pin must not be left floating. (Adjustable version only.)
GND	4	12	—	Ground
IN	5	5,6,7,8	I	Unregulated input to the device.
NC	—	2, 3,4, 13,14,17	O	No connection. This pin can be left floating or connected to GND to allow better thermal contact to the top-side plane.
OUT	3	1, 18, 19, 20	O	Regulated output voltage. No capacitor is required on this pin for stability.
PAD/TAB	—	—	—	Solder to the ground plane for increased thermal performance.
PG	—	9	O	Power-good (PG) is an open-drain, active-high output that indicates the status of V_OUT. When V_OUT exceeds the PG trip threshold, the PG pin goes into a high-impedance state. When V_OUT is below this threshold the pin is driven to a low-impedance state. Connect a pullup resistor from 10kΩ to 1MΩ from this pin to a supply up to 5.5V. The supply can be higher than the input voltage. Alternatively, the PG pin can be left floating if output monitoring is not necessary.
SNS	2	16	I	This pin is the sense connection to the load device. This pin must be connected to V_OUT and must not be left floating. (Fixed versions only.)
SS	1	15	—	Soft-start pin. A capacitor connected on this pin to ground sets the start-up time. If this pin is left floating, the regulator output soft-start ramp time is typically 100μs.

(1) I = Input; O = Output;

(2) The RGR and KTW package are only for the legacy device.

5 Specifications

5.1 Absolute Maximum Ratings

over operating temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
V_IN, V_BIAS	Input voltage	–0.3	6	V
V_EN	Enable voltage	–0.3	6	V
V_PG	Power good voltage	–0.3	6	V
I_PG	PG sink current	0	1.5	mA
V_SS	Soft-start voltage	–0.3	6	V
V_FB	Feedback voltage	–0.3	6	V
V_OUT	Output voltage	–0.3	V_IN + 0.3	V
I_OUT	Maximum output current	Internally limited
	Output short-circuit duration	Indefinite
P_DISS	Continuous total power dissipation	See Thermal Information
T_J	Junction Temperature (Legacy Chip)	–40	125	°C
T_J	Junction Temperature (New Chip)	–40	150	°C
T_stg	Storage Temperature	–55	150	°C

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

5.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
V_IN	Input supply voltage	V_OUT + V_DO (V_IN)	V_OUT + 0.3	5.5	V
V_EN	Enable supply voltage		V_IN	5.5	V
V_BIAS⁽¹⁾	BIAS supply voltage	V_OUT + V_DO (V_BIAS)⁽²⁾	V_OUT + 1.6⁽²⁾	5.5	V
V_OUT	Output voltage	0.8		3.6	V
I_OUT	Output current	0		1.5	A
C_OUT	Output capacitor (legacy chip)	0			µF
C_OUT	Output capacitor (new chip)	2.2			µF
C_IN	Input capacitor⁽³⁾	1			µF
C_BIAS	Bias capacitor	0.1	1		µF
T_J	Operating junction temperature	–40		125	℃

(1) BIAS supply is required when V_IN is below V_OUT + V_DO(V_BIAS).

(2) V_BIAS has a minimum voltage of 2.7 V or V_OUT + V_DO (V_BIAS), whichever is higher (new chip).

(3) If V_IN and V_BIAS are connected to the same supply, the recommended minimum capacitor for the supply is 4.7 μF.

5.4 Thermal Information

THERMAL METRIC ⁽¹⁾		TPS742				UNIT
		RGW (VQFN) (legacy chip)	RGW (VQFN) (new chip)	RGR (VQFN)	KTW (DDPAK/TO-263)
		20 PINS	20 PINS	20 PINS	7 PINS
R_θJA	Junction-to-ambient thermal resistance	35.4	34.7	44.2	47.2	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	32.4	31	50.3	63.7	°C/W
R_θJB	Junction-to-board thermal resistance	14.7	13.5	19.6	19.5	°C/W
ψ_JT	Junction-to-top characterization parameter	0.4	1.4	0.7	4.2	°C/W
ψ_JB	Junction-to-board characterization parameter	14.8	13.5	17.8	19.4	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	3.9	3.6	4.3	3.3	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note.

5.5 Electrical Characteristics

at V_EN = 1.1 V, V_IN = V_OUT + 0.3 V, C_BIAS = 0.1 μF, C_IN = C_OUT = 10 μF, I_OUT = 50 mA, V_BIAS = 5.0 V, and T_J = –40°C to 125°C, (unless otherwise noted); typical values are at T_J = 25°C

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_IN	Input voltage range		V_OUT + V_DO		5.5	V
V_BIAS	BIAS pin voltage range		2.375		5.25	V
V_REF	Internal reference	T_J= 25℃	0.796	0.8	0.804	V
V_OUT	Output voltage	V_IN= 5V, I_OUT= 1.5A, V_BIAS= 5V	V_REF		3.6	V
V_OUT	Accuracy ⁽¹⁾	2.375V ≤ V_BIAS ≤ 5.25V, V_OUT + 1.62V ≤ V_BIAS 50mA ≤ I_OUT ≤ 1.5A	-1	±0.2	1	%
ΔV_OUT(ΔVIN)	Line regulation	V_{OUT (NOM)}+ 0.3V ≤ V_IN ≤ 5.5V, VQFN		0.0005	0.05	%/V
ΔV_OUT(ΔVIN)	Line regulation	V_{OUT (NOM)}+ 0.3V ≤ V_IN ≤ 5.5V, DDPAK/TO-263		0.0005	0.06	%/V
ΔV_OUT(ΔIOUT)	Load regulation	0 mA ≤ I_OUT ≤ 50mA (Legacy Chip)		0.013		%/mA
		50 mA ≤ I_OUT ≤ 1.5 A (Legacy Chip)		0.04		%/A
		50 mA ≤ I_OUT ≤ 1.5 A (New Chip)		0.09		%/A
V_DO	V_IN dropout voltage⁽²⁾	I_OUT = 1.5 A, V_BIAS – V_{OUT (NOM)} ≥ 1.62 V, VQFN		55	100	mV
	V_IN dropout voltage⁽²⁾	I_OUT = 1.5 A, V_BIAS – V_{OUT (NOM)} ≥ 1.62 V, DDPAK/TO-263 (Legacy chip only)		60	120	mV
	V_BIAS dropout voltage⁽²⁾	I_OUT = 1.5A, V_IN = V_BIAS (Legacy Chip)			1.4	V
	V_BIAS dropout voltage⁽²⁾	I_OUT = 1.5A, V_IN = V_BIAS (New Chip)			1.43	V
I_CL	Current limit	V_OUT = 80% × V_OUT(nom),(Legacy Chip)	1.8		4	A
I_CL	Current limit	V_OUT = 80% × V_OUT(nom),(New Chip)	2		5.5	A
I_BIAS	BIAS pin current	I_OUT= 0mA to 1.5A (Legacy Chip)		2	4	mA
I_BIAS	BIAS pin current	I_OUT= 0mA to 1.5A (New Chip)		1	2	mA
I_SHDN	Shutdown supply current (I_GND)	V_EN ≤ 0.4V (Legacy Chip)		1	100	µA
I_SHDN	Shutdown supply current (I_GND)	V_EN ≤ 0.4V, (New Chip)		0.85	2.75	µA
I_FB	Feedback pin current ⁽³⁾	I_OUT= 50mA to 1.5A (Legacy Chip)	–250	68	250	nA
I_FB	Feedback pin current ⁽³⁾	I_OUT= 50mA to 1.5A (New Chip)	–30	0.15	30	nA
PSRR	Power-supply rejection (V_IN to V_OUT)	1 kHz, I_OUT = 1.5 A, V_IN = 1.8 V, V_OUT = 1.5 V (Legacy Chip)		73		dB
		1 kHz, I_OUT = 1.5 A, V_IN = 1.8 V, V_OUT = 1.5 V (New Chip)		60
		300 kHz, I_OUT = 1.5 A, V_IN = 1.8 V, V_OUT = 1.5 V (Legacy Chip)		42
		300 kHz, I_OUT = 1.5 A, V_IN = 1.8 V, V_OUT = 1.5 V (New Chip)		30
	Power-supply rejection (V_BIAS to V_OUT)	1kHz, I_OUT = 1.5A, V_IN = 1.8V, V_OUT = 1.5V (Legacy Chip)		62
		1kHz, I_OUT = 1.5A, V_IN = 1.8V, V_OUT = 1.5V (New Chip)		59
		300kHz, I_OUT = 1.5A, V_IN = 1.8V, V_OUT = 1.5V		50
V_n	Output noise voltage	BW = 100Hz to 100kHz, I_OUT = 1.5A, C_SS = 1nF (Legacy Chip)		16		μVrms x Vout
V_n	Output noise voltage	BW = 100 Hz to 100 kHz, I_OUT = 3A, C_SS = 1nF (New Chip)		20		μVrms x Vout
V_TRAN	%V_OUTdroop during load transient	I_OUT= 50mA to 1.5A at 1A/µs, C_OUT=none (Legacy Chip)		3.5		%V_OUT
V_TRAN	%V_OUTdroop during load transient	I_OUT= 50mA to 1.5A at 1A/µs, C_OUT=2.2µF (New Chip)		1.7		%V_OUT
t_STR	Minimum start-up time	R_LOAD for I_OUT = 1.5A, C_SS = open (Legacy Chip)		100		µs
t_STR	Minimum start-up time	R_LOAD for I_OUT = 1.0A, C_SS = open (New Chip)		250		µs
I_SS	Soft-start charging current	V_SS = 0.4V, I_OUT = 0mA (Legacy Chip)	0.500	0.730	1	µA
I_SS	Soft-start charging current	V_SS = 0.4V, I_OUT = 0mA (New Chip)	0.300	0.530	0.800	µA
V_EN(hi)	Enable input high level		1.1		5.5	V
V_EN(lo)	Enable input low level		0		0.4	V
V_EN(hys)	Enable pin hysteresis	(Legacy Chip)		50		mV
V_EN(hys)	Enable pin hysteresis	(New Chip)		55		mV
V_EN(dg)	Enable pin deglitch time			20		µs
I_EN	Enable pin current	V_EN = 5V (Legacy Chip)		0.1	1	µA
I_EN	Enable pin current	V_EN = 5V (New Chip)		0.1	0.25	µA
V_IT	PG trip threshold	V_OUT decreasing (Legacy Chip)	86.5	90	93.5	%V_OUT
V_IT	PG trip threshold	V_OUT decreasing (New Chip)	85	90	94	%V_OUT
V_HYS	PG trip hysteresis	(Legacy Chip)		3		%V_OUT
V_HYS	PG trip hysteresis	(New Chip)		2.5		%V_OUT
V_PG(lo)	PG output low voltage	I_PG = 1 mA (sinking), V_OUT < V_IT (Legacy Chip)			0.3	V
V_PG(lo)	PG output low voltage	I_PG = 1 mA (sinking), V_OUT < V_IT (New Chip)			0.12	V
I_PG(lkg)	PG leakage current	V_PG = 5.25 V, V_OUT > V_IT (Legacy Chip)		0.03	1	µA
I_PG(lkg)	PG leakage current	V_PG = 5.25 V, V_OUT > V_IT (New Chip)		0.001	0.05	µA
T_J	Operating junction temperature		–40		125	℃
T_SD	Thermal shutdown temperature	Shutdown, temperature increasing (Legacy Chip)		155		℃
		Shutdown, temperature increasing (New Chip)		165
		Reset, temperature decreasing		140

(1) For adjustable devices tested at 0.8V, resistor tolerance is not taken into account.

(2) Dropout is defined as the voltage from the input to V_OUT when V_OUT is 2% below nominal.

(3) I_FB current flow is out of the device.

5.6 Typical Characteristics

at T_J = 25°C, V_OUT = 1.5V, V_IN = V_OUT(NOM) + 0.3V, V_BIAS = 3.3V (legacy chip), V_BIAS = 5.0V (new chip), I_OUT = 50mA, V_EN = V_IN, C_IN = 1μF, C_BIAS = 4.7μF, C_SS = 0.01μF (legacy chip), and C_OUT = 10μF (unless otherwise noted)

Legacy chip

Figure 5-1 Load Regulation

Legacy chip

Figure 5-3 Load Regulation

Legacy chip

Figure 5-5 Line Regulation

TPS74201 VIN Dropout Voltage vs IOUT and Temperature
(TJ)

Legacy chip

Figure 5-7 V_IN Dropout Voltage vs I_OUT and Temperature (T_J)

TPS74201 VIN Dropout Voltage vs VBIAS – VOUT
and Temperature (TJ)

Legacy chip

Figure 5-9 V_IN Dropout Voltage vs V_BIAS – V_OUT and Temperature (T_J)

TPS74201 VBIAS Dropout Voltage vs IOUT and
Temperature

Legacy chip

Figure 5-11 V_BIAS Dropout Voltage vs I_OUT and Temperature

Legacy chip

Figure 5-13 V_BIAS PSRR vs Frequency

Legacy chip

Figure 5-15 V_IN PSRR vs Frequency

New chip

Figure 5-17 V_IN PSRR vs Frequency

New chip

Figure 5-19 V_IN PSRR vs (V_IN – V_OUT)

New chip

Figure 5-21 Noise Spectral Density

TPS74201 BIAS
Pin Current vs Output Current and Temperature (TJ)

New chip

Figure 5-23 BIAS Pin Current vs Output Current and Temperature (T_J)

TPS74201 BIAS
Pin Current vs VBIAS and Temperature (TJ)

New chip

Figure 5-25 BIAS Pin Current vs V_BIAS and Temperature (T_J)

TPS74201 Soft-Start Charging Current (ISS) vs Temperature

Legacy chip

Figure 5-27 Soft-Start Charging Current (I_SS) vs Temperature

TPS74201 Low-Level PG Voltage vs PG Current

Legacy chip

Figure 5-29 Low-Level PG Voltage vs PG Current

Legacy chip

Figure 5-31 V_BIAS Line Transient (1.5A)

Legacy chip

Figure 5-33 V_IN Line Transient

Legacy chip

Figure 5-35 Output Load Transient Response

Legacy chip

Figure 5-37 Turnon Response

Legacy chip

Figure 5-39 Power-Up, Power-Down

Legacy chip

Figure 5-41 Output Short-Circuit Recovery

New chip

Figure 5-2 Load Regulation at Light Load

New chip

Figure 5-4 Load Regulation

New chip

Figure 5-6 Line Regulation

New chip

Figure 5-8 V_IN Dropout Voltage vs I_OUT and Temperature (T_J)

Legacy chip

Figure 5-10 V_IN Dropout Voltage vs V_BIAS – V_OUT and Temperature (T_J)

TPS74201 VBIAS Dropout Voltage vs IOUT and Temperature
(TJ)

New chip

Figure 5-12 V_BIAS Dropout Voltage vs I_OUT and Temperature (T_J)

New chip

Figure 5-14 V_BIAS PSRR vs Frequency

Legacy chip

Figure 5-16 V_IN PSRR vs Frequency

Legacy chip

Figure 5-18 V_IN PSRR vs V_IN – V_OUT

Legacy chip

Figure 5-20 Noise Spectral Density

Legacy chip

Figure 5-22 I_BIAS vs I_OUT and Temperature

Legacy chip

Figure 5-24 I_BIAS vs V_BIAS and V_OUT

Legacy chip

Figure 5-26 I_BIAS Shutdown vs Temperature

TPS74201 Soft-Start Charging Current (ISS) vs Temperature
(TJ)

New chip

Figure 5-28 Soft-Start Charging Current (I_SS) vs Temperature (T_J)

TPS74201 Low-Level PG Voltage vs Current

New chip

Figure 5-30 Low-Level PG Voltage vs Current

New chip

Figure 5-32 V_BIAS Line Transient

New chip

Figure 5-34 V_IN Line Transient

New chip

Figure 5-36 Output Load Transient Response

New chip

Figure 5-38 Turn-On Response

New chip

Figure 5-40 Power-Up, Power-Down

6 Detailed Description

6.1 Overview

The TPS742 belongs to a family of generation ultra-low dropout regulators that feature soft-start and tracking capabilities. These regulators use a low current bias input to power all internal control circuitry, allowing the NMOS pass transistor to regulate very low input and output voltages.

The use of an NMOS-pass transistor offers several critical advantages for many applications. Unlike a PMOS topology device, the output capacitor has little effect on loop stability. This architecture allows the TPS742 devices to be stable with any output capacitor ≥ 2.2μF. Transient response is also superior to PMOS topologies, particularly for low V_IN applications.

The TPS742 devices feature a programmable voltage-controlled soft-start circuit that provides a smooth, monotonic start-up and limits start-up inrush currents that can be caused by large capacitive loads. A power-good (PG) output is available to allow supply monitoring and sequencing of other supplies. An enable (EN) pin with hysteresis and deglitch allows slow-ramping signals to be used for sequencing the device. The low V_IN and V_OUT capability allows for inexpensive, easy-to-design, and efficient linear regulation between the multiple supply voltages often present in processor intensive systems.