SLVSCJ5B
December 2015 – June 2020
TPS7H3301-SP
PRODUCTION DATA.
1
Features
2
Applications
3
Description
Standard DDR Application
4
Revision History
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
VTT/VO Sink and Source Regulator
7.3.2
Reference Input (VDDQSNS)
7.3.3
Reference Output (VTTREF)
7.3.4
EN Control (EN)
7.3.5
Power-Good Function (PGOOD)
7.3.6
VTT Current Protection
7.3.7
VIN UVLO Protection
7.3.8
Thermal Shutdown
7.4
Device Functional Modes
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
VDD/VIN Capacitor
8.2.2.2
VLDO Input Capacitor
8.2.2.3
VTT Output Capacitor
8.2.2.4
VTTSNS Connection
8.2.2.5
Low VIN Applications
8.2.2.6
S3 and Pseudo-S5 Support
8.2.2.7
Tracking Startup and Shutdown
8.2.2.8
Output Tolerance Consideration for VTT DIMM or Module Applications
8.2.2.9
LDO Design Guidelines
8.2.3
Application Curve
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
10.3
Thermal Considerations
11
Device and Documentation Support
11.1
Device Support
11.1.1
Third-Party Products Disclaimer
11.2
Documentation Support
11.2.1
Related Documentation
11.3
Receiving Notification of Documentation Updates
11.4
Support Resources
11.5
Trademarks
11.6
Electrostatic Discharge Caution
11.7
Glossary
12
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
HKR|16
MCDF012C
Thermal pad, mechanical data (Package|Pins)
Orderable Information
slvscj5b_oa
slvscj5b_pm
1
Features
5962R14228
(1)
:
Radiation hardness assurance (RHA) qualified to total ionizing dose (TID) 100 krad(Si)
Single event latch-up (SEL), single event gate rupture (SEGR), single event burnout (SEB) immune to LET = 70 MeV-cm
2
/mg
(2)
Single event transient (SET), single event functional interrupt (SEFI), and single event upset (SEU) characterized to 70 MeV-cm
2
/mg
(2)
Supports DDR, DDR2, DDR3, DDR3L, and DDR4 termination applications
Input voltage: supports a 2.5-V and 3.3-V rail
(3)
Separate low-voltage input (VLDOIN) down to
0.9 V for improved power efficiency
(3)
3-A sink and source termination regulator includes droop compensation
Enable input and power-good output for power supply sequencing
VTT termination regulator
Output voltage range: 0.5 to 1.75 V
3-A sink and source current
Integrated precision voltage divider network with sense input
Remote sensing (VTTSNS)
VTTREF buffered reference
±15-mV accuracy
±10-mA sink and source current
Undervoltage lockout (UVLO) and overcurrent limit (OCL) functionality integrated