SLWS224E August   2010  – January 2016 TRF372017

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Conditions
    3. 6.3 Thermal Information
    4. 6.4 Electrical Characteristics
    5. 6.5 Timing Requirements - SPI: Writing Phase
    6. 6.6 Timing Requirements - SPI: Read-Back Phase
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Integer and Fractional Mode Selection
      2. 7.3.2  Description of PLL Structure
        1. 7.3.2.1 Selecting PLL Divider Values
        2. 7.3.2.2 Setup Example for Integer Mode
        3. 7.3.2.3 Setup Example for Fractional Mode
      3. 7.3.3  Fractional Mode Setup
      4. 7.3.4  Selecting the VCO and VCO Frequency Control
      5. 7.3.5  External VCO
      6. 7.3.6  VCO Test Mode
      7. 7.3.7  Lock Detect
      8. 7.3.8  Tx Divider
      9. 7.3.9  LO Divider
      10. 7.3.10 Mixer
      11. 7.3.11 Disabling Outputs
      12. 7.3.12 Power Supply Distribution
      13. 7.3.13 Carrier Feedthrough Cancellation
      14. 7.3.14 Internal Baseband Bias Voltage Generation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Powersave Mode
    5. 7.5 Register Maps
      1. 7.5.1 Serial Interface Programming Registers Definition
        1. 7.5.1.1 PLL SPI Registers
          1. 7.5.1.1.1 Register 1
          2. 7.5.1.1.2 Register 2
          3. 7.5.1.1.3 Register 3
          4. 7.5.1.1.4 Register 4
          5. 7.5.1.1.5 Register 5
          6. 7.5.1.1.6 Register 6
          7. 7.5.1.1.7 Register 7
        2. 7.5.1.2 Readback Mode
          1. 7.5.1.2.1 Readback From the Internal Registers Banks
            1. 7.5.1.2.1.1 Register 0 Write
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 DAC Interfacing With External Baseband Bias Voltage
        2. 8.2.2.2 DAC Interface Using Internal VCM Generation
        3. 8.2.2.3 LO Outputs
        4. 8.2.2.4 Loop Filter
        5. 8.2.2.5 ESD Sensitivity
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Fully Integrated PLL/VCO and IQ Modulator
  • LO Frequency from 300 MHz to 4.8 GHz
  • 76-dBc Single-Carrier WCDMA ACPR at –8-dBm Channel Power
  • OIP3 of 26 dBm
  • P1dB of 11.5 dBm
  • Integer/Fractional PLL
  • Phase Noise –132 dBc/Hz
    (at 1 MHz, fVCO of 2.3 GHz)
  • Low Noise Floor: –160 dBm/Hz
  • Input Reference Frequency Range: Up to
    160 MHz
  • VCO Frequency Divided by 1-2-4-8 Output

2 Applications

  • Wireless Infrastructure
    • CDMA: IS95, UMTS, CDMA2000, TD-SCDMA
    • TDMA: GSM, IS-136, EDGE/UWC-136
    • LTE
  • Wireless Local Loop
  • Point-to-Point Wireless Access
  • Wireless MAN Wideband Transceivers

3 Description

TRF372017 is a high-performance, direct up-conversion device, integrating a high-linearity, low-noise IQ modulator and an integer-fractional PLL/VCO. The VCO uses integrated frequency dividers to achieve a wide, continuous tuning range of 300 MHz to 4800 MHz. The LO is available as an output with independent frequency dividers. The device also accepts input from an external LO or VCO. The modulator baseband inputs can be biased either internally or externally. Internal DC offset adjustment enables carrier cancellation. The device is controlled through a 3-wire serial programming interface (SPI). A control pin invokes power-save mode to reduce power consumption while keeping the VCO locked for fast start-up.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
TRF372017 VQFN (48) 7.00 mm × 7.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

spacing

Block Diagram

TRF372017 fbd_lws221.gif