Altium

Design Rule Verification Report

Date: 9/25/2024
Time: 3:43:45 PM
Elapsed Time: 00:00:02
Filename: C:\Users\a0500859\Downloads\Lierda_HV3PHINV_response\PMP_PCB_9_25\E1\MCU155E1\Sources\TIEVM-MC-MODULE-F280013x.PcbDoc
Warnings: 0
Rule Violations: 0

Summary

Warnings Count
Total 0

Rule Violations Count
Clearance Constraint (Gap=3mm) (InNetClass('LV Signal')),(InNetClass('ACL')) 0
Clearance Constraint (Gap=3mm) (InNetClass('V_BUS')),(InNetClass('ACL')) 0
Clearance Constraint (Gap=6mm) (InNetClass('Isolation')),(not InNetClass('Isolation') and (not OnLayer('Keep-Out Layer'))) 0
Clearance Constraint (Gap=3mm) (InNetClass('LV Signal')),(InNetClass('ACN')) 0
Clearance Constraint (Gap=2mm) (InNetClass('ACL')),(InNetClass('ACN')) 0
Clearance Constraint (Gap=1.5mm) (InNetClass('V_BUS')),(InNetClass('ACN')) 0
Clearance Constraint (Gap=0.2mm) (All),(not HasFootprint('fiducial10-20') or (InComponent('J1') or InComponent('J2') or InComponent('J3') or InComponent('J4') )) 0
Clearance Constraint (Gap=0.19mm) ((InComponent('J1') or InComponent('J2') or InComponent('J3') or InComponent('J4') ) and not HasFootprint('fiducial10-20')),(All) 0
Clearance Constraint (Gap=3mm) (InNetClass('HV')),(InNetClass('LV_Signal')) 0
Clearance Constraint (Gap=0.15mm) (not IsVia and OnLayer('Multi-Layer') and not InComponent('J1') and not InComponent('J2') and not InComponent('J3') and not InComponent('J4') and not InComponent('J12') and PadIsPlated),(InSMTComponent and OnLayer('Bottom Layer') and not HasFootprint('TP_SM_1MM')) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Modified Polygon (Allow modified: No), (Allow shelved: No) 0
Power Plane Connect Rule(Direct Connect )(Expansion=0.254mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All) 0
Total 0