/**
 * Note: This file was auto-generated by TI PinMux on 3/22/2019 at 11:31:11 AM.
 *
 * \file devicetree.txt
 *
 * \brief This file should only be used as a reference! This file contains
 *  register configuration information for the AM57xx Control Module. Two
 *  formats are provided in this file. The device tree (.dts) format WHICH 
 *  MAY CHANGE BETWEEN LINUX KERNEL VERSIONS and a generic format. For 
 *  summarization and description of the pad register bits refer to the
 *  "Control Module" chapter of the device Data Manual. This file should only
 *  be used as a reference. Some pins and/or peripherals, depending on your
 *  use case, may need additional configuration. Only MMC modes are exported
 *  here. All other pad configuration must be done by u-boot. 
 *
**/


/* * DEVICE TREE FORMAT PADCONF * */

&dra7_pmx_core {

	mmc1_pins_ds: pinmux_mmc1_pins_ds {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc1_clk.mmc1_clk */
			DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc1_cmd.mmc1_cmd */
			DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc1_dat0.mmc1_dat0 */
			DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc1_dat1.mmc1_dat1 */
			DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc1_dat2.mmc1_dat2 */
			DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc1_dat3.mmc1_dat3 */
		>;
	};

	mmc1_pins_hs: pinmux_mmc1_pins_hs {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc1_clk.mmc1_clk */
			DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc1_cmd.mmc1_cmd */
			DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc1_dat0.mmc1_dat0 */
			DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc1_dat1.mmc1_dat1 */
			DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc1_dat2.mmc1_dat2 */
			DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc1_dat3.mmc1_dat3 */
		>;
	};

	mmc1_pins_sdr12: pinmux_mmc1_pins_sdr12 {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc1_clk.mmc1_clk */
			DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc1_cmd.mmc1_cmd */
			DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc1_dat0.mmc1_dat0 */
			DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc1_dat1.mmc1_dat1 */
			DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc1_dat2.mmc1_dat2 */
			DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc1_dat3.mmc1_dat3 */
		>;
	};

	mmc1_pins_sdr25: pinmux_mmc1_pins_sdr25 {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc1_clk.mmc1_clk */
			DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc1_cmd.mmc1_cmd */
			DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc1_dat0.mmc1_dat0 */
			DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc1_dat1.mmc1_dat1 */
			DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc1_dat2.mmc1_dat2 */
			DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) 	/* mmc1_dat3.mmc1_dat3 */
		>;
	};

	mmc1_pins_ddr50: pinmux_mmc1_pins_ddr50 {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) 	/* mmc1_clk.mmc1_clk */
			DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) 	/* mmc1_cmd.mmc1_cmd */
			DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) 	/* mmc1_dat0.mmc1_dat0 */
			DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) 	/* mmc1_dat1.mmc1_dat1 */
			DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) 	/* mmc1_dat2.mmc1_dat2 */
			DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) 	/* mmc1_dat3.mmc1_dat3 */
		>;
	};

	mmc1_pins_sdr104: pinmux_mmc1_pins_sdr104 {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) 	/* mmc1_clk.mmc1_clk */
			DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) 	/* mmc1_cmd.mmc1_cmd */
			DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) 	/* mmc1_dat0.mmc1_dat0 */
			DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) 	/* mmc1_dat1.mmc1_dat1 */
			DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) 	/* mmc1_dat2.mmc1_dat2 */
			DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) 	/* mmc1_dat3.mmc1_dat3 */
		>;
	};

	mmc1_pins_sdr50: pinmux_mmc1_pins_sdr50 {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) 	/* mmc1_clk.mmc1_clk */
			DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) 	/* mmc1_cmd.mmc1_cmd */
			DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) 	/* mmc1_dat0.mmc1_dat0 */
			DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) 	/* mmc1_dat1.mmc1_dat1 */
			DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) 	/* mmc1_dat2.mmc1_dat2 */
			DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) 	/* mmc1_dat3.mmc1_dat3 */
		>;
	};

	mmc2_pins_hs: pinmux_mmc2_pins_hs {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) 	/* gpmc_a23.mmc2_clk */
			DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) 	/* gpmc_cs1.mmc2_cmd */
			DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) 	/* gpmc_a24.mmc2_dat0 */
			DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) 	/* gpmc_a25.mmc2_dat1 */
			DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) 	/* gpmc_a26.mmc2_dat2 */
			DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) 	/* gpmc_a27.mmc2_dat3 */
			DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) 	/* gpmc_a19.mmc2_dat4 */
			DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) 	/* gpmc_a20.mmc2_dat5 */
			DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) 	/* gpmc_a21.mmc2_dat6 */
			DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) 	/* gpmc_a22.mmc2_dat7 */
		>;
	};

	mmc2_pins_std: pinmux_mmc2_pins_std {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) 	/* gpmc_a23.mmc2_clk */
			DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) 	/* gpmc_cs1.mmc2_cmd */
			DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) 	/* gpmc_a24.mmc2_dat0 */
			DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) 	/* gpmc_a25.mmc2_dat1 */
			DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) 	/* gpmc_a26.mmc2_dat2 */
			DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) 	/* gpmc_a27.mmc2_dat3 */
			DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) 	/* gpmc_a19.mmc2_dat4 */
			DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) 	/* gpmc_a20.mmc2_dat5 */
			DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) 	/* gpmc_a21.mmc2_dat6 */
			DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) 	/* gpmc_a22.mmc2_dat7 */
		>;
	};

	mmc2_pins_ddr: pinmux_mmc2_pins_ddr {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) 	/* gpmc_a23.mmc2_clk */
			DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) 	/* gpmc_cs1.mmc2_cmd */
			DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) 	/* gpmc_a24.mmc2_dat0 */
			DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) 	/* gpmc_a25.mmc2_dat1 */
			DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) 	/* gpmc_a26.mmc2_dat2 */
			DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) 	/* gpmc_a27.mmc2_dat3 */
			DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) 	/* gpmc_a19.mmc2_dat4 */
			DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) 	/* gpmc_a20.mmc2_dat5 */
			DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) 	/* gpmc_a21.mmc2_dat6 */
			DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) 	/* gpmc_a22.mmc2_dat7 */
		>;
	};

	mmc2_pins_hs200: pinmux_mmc2_pins_hs200 {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) 	/* gpmc_a23.mmc2_clk */
			DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) 	/* gpmc_cs1.mmc2_cmd */
			DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) 	/* gpmc_a24.mmc2_dat0 */
			DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) 	/* gpmc_a25.mmc2_dat1 */
			DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) 	/* gpmc_a26.mmc2_dat2 */
			DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) 	/* gpmc_a27.mmc2_dat3 */
			DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) 	/* gpmc_a19.mmc2_dat4 */
			DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) 	/* gpmc_a20.mmc2_dat5 */
			DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) 	/* gpmc_a21.mmc2_dat6 */
			DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) 	/* gpmc_a22.mmc2_dat7 */
		>;
	};

};


/* * DEVICE TREE FORMAT IODELAY * */

&dra7_iodelay_core {
// for linux kernel 4.4 / processor sdk 3.x
	mmc1_iodelay_ddr50_rev20_conf: mmc1_iodelay_ddr50_rev20_conf {
		pinctrl-single,pins = <
			0x618 (A_DELAY(588) | G_DELAY(0)) 	/* CFG_MMC1_CLK_IN */
			0x620 (A_DELAY(1230) | G_DELAY(0)) 	/* CFG_MMC1_CLK_OUT */
			0x624 (A_DELAY(1000) | G_DELAY(0)) 	/* CFG_MMC1_CMD_IN */
			0x628 (A_DELAY(0) | G_DELAY(0)) 	/* CFG_MMC1_CMD_OEN */
			0x62C (A_DELAY(0) | G_DELAY(0)) 	/* CFG_MMC1_CMD_OUT */
			0x630 (A_DELAY(1375) | G_DELAY(0)) 	/* CFG_MMC1_DAT0_IN */
			0x634 (A_DELAY(0) | G_DELAY(0)) 	/* CFG_MMC1_DAT0_OEN */
			0x638 (A_DELAY(56) | G_DELAY(0)) 	/* CFG_MMC1_DAT0_OUT */
			0x63C (A_DELAY(1000) | G_DELAY(0)) 	/* CFG_MMC1_DAT1_IN */
			0x640 (A_DELAY(0) | G_DELAY(0)) 	/* CFG_MMC1_DAT1_OEN */
			0x644 (A_DELAY(76) | G_DELAY(0)) 	/* CFG_MMC1_DAT1_OUT */
			0x648 (A_DELAY(1000) | G_DELAY(0)) 	/* CFG_MMC1_DAT2_IN */
			0x64C (A_DELAY(0) | G_DELAY(0)) 	/* CFG_MMC1_DAT2_OEN */
			0x650 (A_DELAY(91) | G_DELAY(0)) 	/* CFG_MMC1_DAT2_OUT */
			0x654 (A_DELAY(1000) | G_DELAY(0)) 	/* CFG_MMC1_DAT3_IN */
			0x658 (A_DELAY(0) | G_DELAY(0)) 	/* CFG_MMC1_DAT3_OEN */
			0x65C (A_DELAY(99) | G_DELAY(0)) 	/* CFG_MMC1_DAT3_OUT */
		>;
	};

	mmc1_iodelay_sdr104_rev20_conf: mmc1_iodelay_sdr104_rev20_conf {
		pinctrl-single,pins = <
			0x620 (A_DELAY(520) | G_DELAY(320)) 	/* CFG_MMC1_CLK_OUT */
			0x628 (A_DELAY(51) | G_DELAY(0)) 	/* CFG_MMC1_CMD_OEN */
			0x62C (A_DELAY(0) | G_DELAY(0)) 	/* CFG_MMC1_CMD_OUT */
			0x634 (A_DELAY(0) | G_DELAY(0)) 	/* CFG_MMC1_DAT0_OEN */
			0x638 (A_DELAY(40) | G_DELAY(0)) 	/* CFG_MMC1_DAT0_OUT */
			0x640 (A_DELAY(363) | G_DELAY(0)) 	/* CFG_MMC1_DAT1_OEN */
			0x644 (A_DELAY(83) | G_DELAY(0)) 	/* CFG_MMC1_DAT1_OUT */
			0x64C (A_DELAY(199) | G_DELAY(0)) 	/* CFG_MMC1_DAT2_OEN */
			0x650 (A_DELAY(98) | G_DELAY(0)) 	/* CFG_MMC1_DAT2_OUT */
			0x658 (A_DELAY(273) | G_DELAY(0)) 	/* CFG_MMC1_DAT3_OEN */
			0x65C (A_DELAY(106) | G_DELAY(0)) 	/* CFG_MMC1_DAT3_OUT */
		>;
	};

	mmc2_iodelay_ddr_rev20_conf: mmc2_iodelay_ddr_rev20_conf {
		pinctrl-single,pins = <
			0x1C8 (A_DELAY(894) | G_DELAY(0)) 	/* CFG_GPMC_A23_IN */
			0x1D0 (A_DELAY(266) | G_DELAY(0)) 	/* CFG_GPMC_A23_OUT */
			0x360 (A_DELAY(0) | G_DELAY(0)) 	/* CFG_GPMC_CS1_IN */
			0x364 (A_DELAY(0) | G_DELAY(0)) 	/* CFG_GPMC_CS1_OEN */
			0x368 (A_DELAY(0) | G_DELAY(0)) 	/* CFG_GPMC_CS1_OUT */
			0x1D4 (A_DELAY(30) | G_DELAY(0)) 	/* CFG_GPMC_A24_IN */
			0x1D8 (A_DELAY(0) | G_DELAY(0)) 	/* CFG_GPMC_A24_OEN */
			0x1DC (A_DELAY(0) | G_DELAY(0)) 	/* CFG_GPMC_A24_OUT */
			0x1E0 (A_DELAY(0) | G_DELAY(0)) 	/* CFG_GPMC_A25_IN */
			0x1E4 (A_DELAY(0) | G_DELAY(0)) 	/* CFG_GPMC_A25_OEN */
			0x1E8 (A_DELAY(0) | G_DELAY(0)) 	/* CFG_GPMC_A25_OUT */
			0x1EC (A_DELAY(23) | G_DELAY(0)) 	/* CFG_GPMC_A26_IN */
			0x1F0 (A_DELAY(0) | G_DELAY(0)) 	/* CFG_GPMC_A26_OEN */
			0x1F4 (A_DELAY(43) | G_DELAY(0)) 	/* CFG_GPMC_A26_OUT */
			0x1F8 (A_DELAY(0) | G_DELAY(0)) 	/* CFG_GPMC_A27_IN */
			0x1FC (A_DELAY(0) | G_DELAY(0)) 	/* CFG_GPMC_A27_OEN */
			0x200 (A_DELAY(0) | G_DELAY(0)) 	/* CFG_GPMC_A27_OUT */
			0x18C (A_DELAY(0) | G_DELAY(0)) 	/* CFG_GPMC_A19_IN */
			0x190 (A_DELAY(0) | G_DELAY(0)) 	/* CFG_GPMC_A19_OEN */
			0x194 (A_DELAY(152) | G_DELAY(0)) 	/* CFG_GPMC_A19_OUT */
			0x1A4 (A_DELAY(119) | G_DELAY(0)) 	/* CFG_GPMC_A20_IN */
			0x1A8 (A_DELAY(0) | G_DELAY(0)) 	/* CFG_GPMC_A20_OEN */
			0x1AC (A_DELAY(206) | G_DELAY(0)) 	/* CFG_GPMC_A20_OUT */
			0x1B0 (A_DELAY(0) | G_DELAY(0)) 	/* CFG_GPMC_A21_IN */
			0x1B4 (A_DELAY(0) | G_DELAY(0)) 	/* CFG_GPMC_A21_OEN */
			0x1B8 (A_DELAY(78) | G_DELAY(0)) 	/* CFG_GPMC_A21_OUT */
			0x1BC (A_DELAY(18) | G_DELAY(0)) 	/* CFG_GPMC_A22_IN */
			0x1C0 (A_DELAY(0) | G_DELAY(0)) 	/* CFG_GPMC_A22_OEN */
			0x1C4 (A_DELAY(2) | G_DELAY(0)) 	/* CFG_GPMC_A22_OUT */
		>;
	};

	mmc2_iodelay_hs200_rev20_conf: mmc2_iodelay_hs200_rev20_conf {
		pinctrl-single,pins = <
			0x1D0 (A_DELAY(730) | G_DELAY(360)) 	/* CFG_GPMC_A23_OUT */
			0x364 (A_DELAY(360) | G_DELAY(0)) 	/* CFG_GPMC_CS1_OEN */
			0x368 (A_DELAY(0) | G_DELAY(120)) 	/* CFG_GPMC_CS1_OUT */
			0x1D8 (A_DELAY(176) | G_DELAY(0)) 	/* CFG_GPMC_A24_OEN */
			0x1DC (A_DELAY(0) | G_DELAY(0)) 	/* CFG_GPMC_A24_OUT */
			0x1E4 (A_DELAY(0) | G_DELAY(0)) 	/* CFG_GPMC_A25_OEN */
			0x1E8 (A_DELAY(0) | G_DELAY(0)) 	/* CFG_GPMC_A25_OUT */
			0x1F0 (A_DELAY(101) | G_DELAY(0)) 	/* CFG_GPMC_A26_OEN */
			0x1F4 (A_DELAY(70) | G_DELAY(0)) 	/* CFG_GPMC_A26_OUT */
			0x1FC (A_DELAY(0) | G_DELAY(0)) 	/* CFG_GPMC_A27_OEN */
			0x200 (A_DELAY(0) | G_DELAY(0)) 	/* CFG_GPMC_A27_OUT */
			0x190 (A_DELAY(0) | G_DELAY(0)) 	/* CFG_GPMC_A19_OEN */
			0x194 (A_DELAY(285) | G_DELAY(0)) 	/* CFG_GPMC_A19_OUT */
			0x1A8 (A_DELAY(231) | G_DELAY(0)) 	/* CFG_GPMC_A20_OEN */
			0x1AC (A_DELAY(189) | G_DELAY(0)) 	/* CFG_GPMC_A20_OUT */
			0x1B4 (A_DELAY(39) | G_DELAY(0)) 	/* CFG_GPMC_A21_OEN */
			0x1B8 (A_DELAY(0) | G_DELAY(120)) 	/* CFG_GPMC_A21_OUT */
			0x1C0 (A_DELAY(91) | G_DELAY(0)) 	/* CFG_GPMC_A22_OEN */
			0x1C4 (A_DELAY(0) | G_DELAY(70)) 	/* CFG_GPMC_A22_OUT */
		>;
	};

};



/* * GENERIC FORMAT PADCONF * */

	/* MMC1_PINS_DS */
	0x1754	0x60000	W6	CTRL_CORE_PAD_MMC1_CLK	mmc1_clk	mmc1_clk
	0x1758	0x60000	Y6	CTRL_CORE_PAD_MMC1_CMD	mmc1_cmd	mmc1_cmd
	0x175C	0x60000	AA6	CTRL_CORE_PAD_MMC1_DAT0	mmc1_dat0	mmc1_dat0
	0x1760	0x60000	Y4	CTRL_CORE_PAD_MMC1_DAT1	mmc1_dat1	mmc1_dat1
	0x1764	0x60000	AA5	CTRL_CORE_PAD_MMC1_DAT2	mmc1_dat2	mmc1_dat2
	0x1768	0x60000	Y3	CTRL_CORE_PAD_MMC1_DAT3	mmc1_dat3	mmc1_dat3
	/* MMC1_PINS_HS */
	0x1754	0x60000	W6	CTRL_CORE_PAD_MMC1_CLK	mmc1_clk	mmc1_clk
	0x1758	0x60000	Y6	CTRL_CORE_PAD_MMC1_CMD	mmc1_cmd	mmc1_cmd
	0x175C	0x60000	AA6	CTRL_CORE_PAD_MMC1_DAT0	mmc1_dat0	mmc1_dat0
	0x1760	0x60000	Y4	CTRL_CORE_PAD_MMC1_DAT1	mmc1_dat1	mmc1_dat1
	0x1764	0x60000	AA5	CTRL_CORE_PAD_MMC1_DAT2	mmc1_dat2	mmc1_dat2
	0x1768	0x60000	Y3	CTRL_CORE_PAD_MMC1_DAT3	mmc1_dat3	mmc1_dat3
	/* MMC1_PINS_SDR12 */
	0x1754	0x60000	W6	CTRL_CORE_PAD_MMC1_CLK	mmc1_clk	mmc1_clk
	0x1758	0x60000	Y6	CTRL_CORE_PAD_MMC1_CMD	mmc1_cmd	mmc1_cmd
	0x175C	0x60000	AA6	CTRL_CORE_PAD_MMC1_DAT0	mmc1_dat0	mmc1_dat0
	0x1760	0x60000	Y4	CTRL_CORE_PAD_MMC1_DAT1	mmc1_dat1	mmc1_dat1
	0x1764	0x60000	AA5	CTRL_CORE_PAD_MMC1_DAT2	mmc1_dat2	mmc1_dat2
	0x1768	0x60000	Y3	CTRL_CORE_PAD_MMC1_DAT3	mmc1_dat3	mmc1_dat3
	/* MMC1_PINS_SDR25 */
	0x1754	0x60000	W6	CTRL_CORE_PAD_MMC1_CLK	mmc1_clk	mmc1_clk
	0x1758	0x60000	Y6	CTRL_CORE_PAD_MMC1_CMD	mmc1_cmd	mmc1_cmd
	0x175C	0x60000	AA6	CTRL_CORE_PAD_MMC1_DAT0	mmc1_dat0	mmc1_dat0
	0x1760	0x60000	Y4	CTRL_CORE_PAD_MMC1_DAT1	mmc1_dat1	mmc1_dat1
	0x1764	0x60000	AA5	CTRL_CORE_PAD_MMC1_DAT2	mmc1_dat2	mmc1_dat2
	0x1768	0x60000	Y3	CTRL_CORE_PAD_MMC1_DAT3	mmc1_dat3	mmc1_dat3
	/* MMC1_PINS_DDR50 */
	0x1754	0x60100	W6	CTRL_CORE_PAD_MMC1_CLK	mmc1_clk	mmc1_clk
	0x1758	0x60100	Y6	CTRL_CORE_PAD_MMC1_CMD	mmc1_cmd	mmc1_cmd
	0x175C	0x60100	AA6	CTRL_CORE_PAD_MMC1_DAT0	mmc1_dat0	mmc1_dat0
	0x1760	0x60100	Y4	CTRL_CORE_PAD_MMC1_DAT1	mmc1_dat1	mmc1_dat1
	0x1764	0x60100	AA5	CTRL_CORE_PAD_MMC1_DAT2	mmc1_dat2	mmc1_dat2
	0x1768	0x60100	Y3	CTRL_CORE_PAD_MMC1_DAT3	mmc1_dat3	mmc1_dat3
	/* MMC1_PINS_SDR104 */
	0x1754	0x60100	W6	CTRL_CORE_PAD_MMC1_CLK	mmc1_clk	mmc1_clk
	0x1758	0x60100	Y6	CTRL_CORE_PAD_MMC1_CMD	mmc1_cmd	mmc1_cmd
	0x175C	0x60100	AA6	CTRL_CORE_PAD_MMC1_DAT0	mmc1_dat0	mmc1_dat0
	0x1760	0x60100	Y4	CTRL_CORE_PAD_MMC1_DAT1	mmc1_dat1	mmc1_dat1
	0x1764	0x60100	AA5	CTRL_CORE_PAD_MMC1_DAT2	mmc1_dat2	mmc1_dat2
	0x1768	0x60100	Y3	CTRL_CORE_PAD_MMC1_DAT3	mmc1_dat3	mmc1_dat3
	/* MMC1_PINS_SDR50 */
	0x1754	0x601F0	W6	CTRL_CORE_PAD_MMC1_CLK	mmc1_clk	mmc1_clk
	0x1758	0x601F0	Y6	CTRL_CORE_PAD_MMC1_CMD	mmc1_cmd	mmc1_cmd
	0x175C	0x601F0	AA6	CTRL_CORE_PAD_MMC1_DAT0	mmc1_dat0	mmc1_dat0
	0x1760	0x601F0	Y4	CTRL_CORE_PAD_MMC1_DAT1	mmc1_dat1	mmc1_dat1
	0x1764	0x601F0	AA5	CTRL_CORE_PAD_MMC1_DAT2	mmc1_dat2	mmc1_dat2
	0x1768	0x601F0	Y3	CTRL_CORE_PAD_MMC1_DAT3	mmc1_dat3	mmc1_dat3
	/* MMC2_PINS_HS */
	0x149C	0x60001	J7	CTRL_CORE_PAD_GPMC_A23	gpmc_a23	mmc2_clk
	0x14B0	0x60001	H6	CTRL_CORE_PAD_GPMC_CS1	gpmc_cs1	mmc2_cmd
	0x14A0	0x60001	J4	CTRL_CORE_PAD_GPMC_A24	gpmc_a24	mmc2_dat0
	0x14A4	0x60001	J6	CTRL_CORE_PAD_GPMC_A25	gpmc_a25	mmc2_dat1
	0x14A8	0x60001	H4	CTRL_CORE_PAD_GPMC_A26	gpmc_a26	mmc2_dat2
	0x14AC	0x60001	H5	CTRL_CORE_PAD_GPMC_A27	gpmc_a27	mmc2_dat3
	0x148C	0x60001	K7	CTRL_CORE_PAD_GPMC_A19	gpmc_a19	mmc2_dat4
	0x1490	0x60001	M7	CTRL_CORE_PAD_GPMC_A20	gpmc_a20	mmc2_dat5
	0x1494	0x60001	J5	CTRL_CORE_PAD_GPMC_A21	gpmc_a21	mmc2_dat6
	0x1498	0x60001	K6	CTRL_CORE_PAD_GPMC_A22	gpmc_a22	mmc2_dat7
	/* MMC2_PINS_STD */
	0x149C	0x60001	J7	CTRL_CORE_PAD_GPMC_A23	gpmc_a23	mmc2_clk
	0x14B0	0x60001	H6	CTRL_CORE_PAD_GPMC_CS1	gpmc_cs1	mmc2_cmd
	0x14A0	0x60001	J4	CTRL_CORE_PAD_GPMC_A24	gpmc_a24	mmc2_dat0
	0x14A4	0x60001	J6	CTRL_CORE_PAD_GPMC_A25	gpmc_a25	mmc2_dat1
	0x14A8	0x60001	H4	CTRL_CORE_PAD_GPMC_A26	gpmc_a26	mmc2_dat2
	0x14AC	0x60001	H5	CTRL_CORE_PAD_GPMC_A27	gpmc_a27	mmc2_dat3
	0x148C	0x60001	K7	CTRL_CORE_PAD_GPMC_A19	gpmc_a19	mmc2_dat4
	0x1490	0x60001	M7	CTRL_CORE_PAD_GPMC_A20	gpmc_a20	mmc2_dat5
	0x1494	0x60001	J5	CTRL_CORE_PAD_GPMC_A21	gpmc_a21	mmc2_dat6
	0x1498	0x60001	K6	CTRL_CORE_PAD_GPMC_A22	gpmc_a22	mmc2_dat7
	/* MMC2_PINS_DDR */
	0x149C	0x60101	J7	CTRL_CORE_PAD_GPMC_A23	gpmc_a23	mmc2_clk
	0x14B0	0x60101	H6	CTRL_CORE_PAD_GPMC_CS1	gpmc_cs1	mmc2_cmd
	0x14A0	0x60101	J4	CTRL_CORE_PAD_GPMC_A24	gpmc_a24	mmc2_dat0
	0x14A4	0x60101	J6	CTRL_CORE_PAD_GPMC_A25	gpmc_a25	mmc2_dat1
	0x14A8	0x60101	H4	CTRL_CORE_PAD_GPMC_A26	gpmc_a26	mmc2_dat2
	0x14AC	0x60101	H5	CTRL_CORE_PAD_GPMC_A27	gpmc_a27	mmc2_dat3
	0x148C	0x60101	K7	CTRL_CORE_PAD_GPMC_A19	gpmc_a19	mmc2_dat4
	0x1490	0x60101	M7	CTRL_CORE_PAD_GPMC_A20	gpmc_a20	mmc2_dat5
	0x1494	0x60101	J5	CTRL_CORE_PAD_GPMC_A21	gpmc_a21	mmc2_dat6
	0x1498	0x60101	K6	CTRL_CORE_PAD_GPMC_A22	gpmc_a22	mmc2_dat7
	/* MMC2_PINS_HS200 */
	0x149C	0x60101	J7	CTRL_CORE_PAD_GPMC_A23	gpmc_a23	mmc2_clk
	0x14B0	0x60101	H6	CTRL_CORE_PAD_GPMC_CS1	gpmc_cs1	mmc2_cmd
	0x14A0	0x60101	J4	CTRL_CORE_PAD_GPMC_A24	gpmc_a24	mmc2_dat0
	0x14A4	0x60101	J6	CTRL_CORE_PAD_GPMC_A25	gpmc_a25	mmc2_dat1
	0x14A8	0x60101	H4	CTRL_CORE_PAD_GPMC_A26	gpmc_a26	mmc2_dat2
	0x14AC	0x60101	H5	CTRL_CORE_PAD_GPMC_A27	gpmc_a27	mmc2_dat3
	0x148C	0x60101	K7	CTRL_CORE_PAD_GPMC_A19	gpmc_a19	mmc2_dat4
	0x1490	0x60101	M7	CTRL_CORE_PAD_GPMC_A20	gpmc_a20	mmc2_dat5
	0x1494	0x60101	J5	CTRL_CORE_PAD_GPMC_A21	gpmc_a21	mmc2_dat6
	0x1498	0x60101	K6	CTRL_CORE_PAD_GPMC_A22	gpmc_a22	mmc2_dat7


/* * GENERIC FORMAT IODELAY * */

	/* MMC1_IODELAY_DDR50 */
	0x618	588	0	CFG_MMC1_CLK_IN	W6
	0x620	1230	0	CFG_MMC1_CLK_OUT	W6

	0x624	1000	0	CFG_MMC1_CMD_IN	Y6
	0x628	0	0	CFG_MMC1_CMD_OEN	Y6
	0x62C	0	0	CFG_MMC1_CMD_OUT	Y6

	0x630	1375	0	CFG_MMC1_DAT0_IN	AA6
	0x634	0	0	CFG_MMC1_DAT0_OEN	AA6
	0x638	56	0	CFG_MMC1_DAT0_OUT	AA6

	0x63C	1000	0	CFG_MMC1_DAT1_IN	Y4
	0x640	0	0	CFG_MMC1_DAT1_OEN	Y4
	0x644	76	0	CFG_MMC1_DAT1_OUT	Y4

	0x648	1000	0	CFG_MMC1_DAT2_IN	AA5
	0x64C	0	0	CFG_MMC1_DAT2_OEN	AA5
	0x650	91	0	CFG_MMC1_DAT2_OUT	AA5

	0x654	1000	0	CFG_MMC1_DAT3_IN	Y3
	0x658	0	0	CFG_MMC1_DAT3_OEN	Y3
	0x65C	99	0	CFG_MMC1_DAT3_OUT	Y3

	/* MMC1_IODELAY_SDR104 */
	0x620	520	320	CFG_MMC1_CLK_OUT	W6

	0x628	51	0	CFG_MMC1_CMD_OEN	Y6
	0x62C	0	0	CFG_MMC1_CMD_OUT	Y6

	0x634	0	0	CFG_MMC1_DAT0_OEN	AA6
	0x638	40	0	CFG_MMC1_DAT0_OUT	AA6

	0x640	363	0	CFG_MMC1_DAT1_OEN	Y4
	0x644	83	0	CFG_MMC1_DAT1_OUT	Y4

	0x64C	199	0	CFG_MMC1_DAT2_OEN	AA5
	0x650	98	0	CFG_MMC1_DAT2_OUT	AA5

	0x658	273	0	CFG_MMC1_DAT3_OEN	Y3
	0x65C	106	0	CFG_MMC1_DAT3_OUT	Y3

	/* MMC2_IODELAY_DDR */
	0x1C8	894	0	CFG_GPMC_A23_IN	J7
	0x1D0	266	0	CFG_GPMC_A23_OUT	J7

	0x360	0	0	CFG_GPMC_CS1_IN	H6
	0x364	0	0	CFG_GPMC_CS1_OEN	H6
	0x368	0	0	CFG_GPMC_CS1_OUT	H6

	0x1D4	30	0	CFG_GPMC_A24_IN	J4
	0x1D8	0	0	CFG_GPMC_A24_OEN	J4
	0x1DC	0	0	CFG_GPMC_A24_OUT	J4

	0x1E0	0	0	CFG_GPMC_A25_IN	J6
	0x1E4	0	0	CFG_GPMC_A25_OEN	J6
	0x1E8	0	0	CFG_GPMC_A25_OUT	J6

	0x1EC	23	0	CFG_GPMC_A26_IN	H4
	0x1F0	0	0	CFG_GPMC_A26_OEN	H4
	0x1F4	43	0	CFG_GPMC_A26_OUT	H4

	0x1F8	0	0	CFG_GPMC_A27_IN	H5
	0x1FC	0	0	CFG_GPMC_A27_OEN	H5
	0x200	0	0	CFG_GPMC_A27_OUT	H5

	0x18C	0	0	CFG_GPMC_A19_IN	K7
	0x190	0	0	CFG_GPMC_A19_OEN	K7
	0x194	152	0	CFG_GPMC_A19_OUT	K7

	0x1A4	119	0	CFG_GPMC_A20_IN	M7
	0x1A8	0	0	CFG_GPMC_A20_OEN	M7
	0x1AC	206	0	CFG_GPMC_A20_OUT	M7

	0x1B0	0	0	CFG_GPMC_A21_IN	J5
	0x1B4	0	0	CFG_GPMC_A21_OEN	J5
	0x1B8	78	0	CFG_GPMC_A21_OUT	J5

	0x1BC	18	0	CFG_GPMC_A22_IN	K6
	0x1C0	0	0	CFG_GPMC_A22_OEN	K6
	0x1C4	2	0	CFG_GPMC_A22_OUT	K6

	/* MMC2_IODELAY_HS200 */
	0x1D0	730	360	CFG_GPMC_A23_OUT	J7

	0x364	360	0	CFG_GPMC_CS1_OEN	H6
	0x368	0	120	CFG_GPMC_CS1_OUT	H6

	0x1D8	176	0	CFG_GPMC_A24_OEN	J4
	0x1DC	0	0	CFG_GPMC_A24_OUT	J4

	0x1E4	0	0	CFG_GPMC_A25_OEN	J6
	0x1E8	0	0	CFG_GPMC_A25_OUT	J6

	0x1F0	101	0	CFG_GPMC_A26_OEN	H4
	0x1F4	70	0	CFG_GPMC_A26_OUT	H4

	0x1FC	0	0	CFG_GPMC_A27_OEN	H5
	0x200	0	0	CFG_GPMC_A27_OUT	H5

	0x190	0	0	CFG_GPMC_A19_OEN	K7
	0x194	285	0	CFG_GPMC_A19_OUT	K7

	0x1A8	231	0	CFG_GPMC_A20_OEN	M7
	0x1AC	189	0	CFG_GPMC_A20_OUT	M7

	0x1B4	39	0	CFG_GPMC_A21_OEN	J5
	0x1B8	0	120	CFG_GPMC_A21_OUT	J5

	0x1C0	91	0	CFG_GPMC_A22_OEN	K6
	0x1C4	0	70	CFG_GPMC_A22_OUT	K6

