Altium

Design Rule Verification Report

Date: 2/26/2024
Time: 12:52:33 PM
Elapsed Time: 00:00:06
Filename: \\xle3090dm44\pds\ReferenceDesigns\PMP23251 thru 23500\PMP23464\Altium\PCB_Project_PMP23464_PCB.PcbDoc
Warnings: 0
Rule Violations: 4

Summary

Warnings Count
Total 0

Rule Violations Count
Clearance Constraint (Gap=1.27mm) (InNetClass('HV')),(Not InNetClass('HV')) 0
Clearance Constraint (Gap=0mm) (((IsTrack Or IsArc) And Not InPoly) And IsFree and IsKeepOut),(((IsTrack Or IsArc) And Not InPoly) And IsFree and IsKeepOut) 0
Clearance Constraint (Gap=3.3mm) (InNet('EARTH')),(Not InNet('EARTH') And Not InNet('12VS')) 0
Clearance Constraint (Gap=0.635mm) (InNetClass('HV')),(InNetClass('MV')) 0
Clearance Constraint (Gap=1.016mm) (OnCopper and InComponentClass('Mounting Holes')),(IsKeepOut) 0
Clearance Constraint (Gap=0.3048mm) (InPolygon),(All) 0
Clearance Constraint (Gap=0.2mm) (All),(All) 0
Clearance Constraint (Gap=0.635mm) (OnCopper and InPoly),(IsKeepOut) 0
Clearance Constraint (Gap=1.905mm) (OnCopper and Not InComponentClass('Logo') and not InComponentClass('FiducialMark') and not InRegion(1000,500,4000,800) and Not IsKeepout),(IsKeepOut) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Width Constraint (Min=0.1524mm) (Max=2.54mm) (Preferred=0.254mm) (All) 0
Routing Layers(All) 0
Routing Via (MinHoleWidth=0.2mm) (MaxHoleWidth=0.33mm) (PreferredHoleWidth=0.2mm) (MinWidth=0.5mm) (MaxWidth=0.6mm) (PreferedWidth=0.5mm) (IsVia and InAnyComponent) 0
Routing Via (MinHoleWidth=0.2mm) (MaxHoleWidth=1.016mm) (PreferredHoleWidth=0.4064mm) (MinWidth=0.508mm) (MaxWidth=1.651mm) (PreferedWidth=0.8636mm) (All) 0
Differential Pairs Uncoupled Length using the Gap Constraints (Min=0.254mm) (Max=2.54mm) (Prefered=0.254mm) and Width Constraints (Min=0.381mm) (Max=0.381mm) (Prefered=0.381mm) (All) 0
Power Plane Connect Rule(Direct Connect )(Expansion=0.254mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All) 0
Minimum Annular Ring (Minimum=0.12446mm) (All) 0
Minimum Annular Ring (Minimum=0.15mm) (IsVia and InAnyComponent) 0
Acute Angle Constraint (Minimum=45.000) (All) 0
Hole Size Constraint (Min=0.1778mm) (Max=6.3754mm) (All) 0
Pads and Vias to follow the Drill pairs settings 0
Hole To Hole Clearance (Gap=0.254mm) (All),(All) 0
Minimum Solder Mask Sliver (Gap=0.0508mm) (All),(All) 0
Minimum Solder Mask Sliver (Gap=0.01778mm) (InComponentClass('Logo')),(InComponentClass('Logo')) 0
Silk To Solder Mask (Clearance=0.0254mm) (All),(All) 3
Silk to Silk (Clearance=0.0254mm) (All),(All) 1
Silk to Silk (Clearance=0mm) ((HasFootprint('Pb-Free_Overlay_Medium') OR HasFootprint('Pb-Free_Overlay_Small'))),((HasFootprint('Pb-Free_Overlay_Medium') OR HasFootprint('Pb-Free_Overlay_Small'))) 0
Net Antennae (Tolerance=0mm) (All) 0
Component Clearance Constraint ( Horizontal Gap = 0.254mm, Vertical Gap = 0.254mm ) (IsThruComponent),(IsSMTComponent) 0
Component Clearance Constraint ( Horizontal Gap = 0.508mm, Vertical Gap = 0.508mm ) (HasFootprint('0201*') or HasFootprint('0402*') or HasFootprint('0508') or HasFootprint('0603*') or HasFootprint('0612') or HasFootprint('0805*') or HasFootprint('0815*') or HasFootprint('0830*') or HasFootprint('1206*') or HasFootprint('1210*') or HasFootprint('1808*') or HasFootprint('1812*') or HasFootprint('1825*') or HasFootprint('2010*') or HasFootprint('2220*') or HasFootprint('2225*') or HasFootprint('2512*') or HasFootprint('2728*') or HasFootprint('3518*')),(HasFootprint('0201*') or HasFootprint('0402*') or HasFootprint('0508') or HasFootprint('0603*') or HasFootprint('0612') or HasFootprint('0805*') or HasFootprint('0815*') or HasFootprint('0830*') or HasFootprint('1206*') or HasFootprint('1210*') or HasFootprint('1808*') or HasFootprint('1812*') or HasFootprint('1825*') or HasFootprint('2010*') or HasFootprint('2220*') or HasFootprint('2225*') or HasFootprint('2512*') or HasFootprint('2728*') or HasFootprint('3518*')) 0
Component Clearance Constraint ( Horizontal Gap = 0.254mm, Vertical Gap = 0.254mm ) (All),(All) 0
Component Clearance Constraint ( Horizontal Gap = 0.254mm, Vertical Gap = 0.254mm ) (IsThruComponent),(IsThruComponent) 0
Component Clearance Constraint ( Horizontal Gap = 0.508mm, Vertical Gap = 0.254mm ) (InComponentClass('Mounting Holes')),(All) 0
Component Clearance Constraint ( Horizontal Gap = 0mm, Vertical Gap = 0mm ) (InComponentClass('Header')),(InComponentClass('Shunt')) 0
Component Clearance Constraint ( Horizontal Gap = 0.508mm, Vertical Gap = 0.254mm ) (InComponentClass('Mounting Holes')),(InComponentClass('FiducialMark')) 0
Component Clearance Constraint ( Horizontal Gap = 0.508mm, Vertical Gap = Infinite ) ((HasFootprint('NY PMS 440 0025 PH'))),((HasFootprint('Keystone_1902C'))) 0
Component Clearance Constraint ( Horizontal Gap = 0.127mm, Vertical Gap = 0.254mm ) (InComponentClass('Logo')),(All) 0
Height Constraint (Min=0mm) (Max=76.2mm) (Prefered=12.7mm) (All) 0
Total 4

Silk To Solder Mask (Clearance=0.0254mm) (All),(All)
Silk To Solder Mask Clearance Constraint: (Collision < 0.0254mm) Between Arc (132.588mm,40.513mm) on Top Overlay And Pad U3-3(134.7254mm,39.529mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.0254mm) Between Pad H1-1(117.366mm,94.428mm) on Multi-Layer And Track (7.366mm,95.028mm)(127.366mm,95.028mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.0254mm) Between Pad H2-1(148.4338mm,90.8466mm) on Multi-Layer And Track (143.4338mm,91.4466mm)(183.4338mm,91.4466mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]

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Silk to Silk (Clearance=0.0254mm) (All),(All)
Silk To Silk Clearance Constraint: (Collision < 0.0254mm) Between Arc (132.588mm,40.513mm) on Top Overlay And Text "I_OPTO" (125.6039mm,40.8518mm) on Top Overlay Silk Text to Silk Clearance [0mm]

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