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High-speed ADCs (≥10 MSPS)

ADC12QJ1600-SP

ACTIVE

Radiation-hardened, 300krad, 12-bit quad-channel 1.6GSPS ADC

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Data sheet

ADC12QJ1600-SP

ACTIVE
Data sheet Order now

Product details

Sample rate (max) (Msps) 1600 Resolution (Bits) 12 Number of input channels 4 Interface type JESD204B, JESD204C Analog input BW (MHz) 6000 Features Ultra High Speed Rating Space Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 1910 Architecture Folding Interpolating SNR (dB) 57.4 ENOB (Bits) 9 SFDR (dB) 64 Operating temperature range (°C) -55 to 125 Input buffer Yes Radiation, TID (typ) (krad) 300 Radiation, SEL (MeV·cm2/mg) 120
Sample rate (max) (Msps) 1600 Resolution (Bits) 12 Number of input channels 4 Interface type JESD204B, JESD204C Analog input BW (MHz) 6000 Features Ultra High Speed Rating Space Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 1910 Architecture Folding Interpolating SNR (dB) 57.4 ENOB (Bits) 9 SFDR (dB) 64 Operating temperature range (°C) -55 to 125 Input buffer Yes Radiation, TID (typ) (krad) 300 Radiation, SEL (MeV·cm2/mg) 120
FCCSP (ALR) 144 100 mm² (10 mm × 10 mm)
  • Radiation Performance:
    • Total Ionizing Dose (TID): 300 krad (Si)
    • Single Event Latchup (SEL): 120 MeV-cm2/mg
    • Single Event Upset (SEU) immune registers
  • ADC Core:
    • Resolution: 12 Bit
    • Maximum sampling rate: 1.6GSPS
    • Non-interleaved architecture
    • Internal dither reduces high-order harmonics
  • Performance specifications (–1dBFS):
    • SNR (100 MHz): 57.4dBFS
    • ENOB (100 MHz): 9.1 Bits
    • SFDR (100 MHz): 64dBc
    • Noise floor (–20dBFS): –147dBFS
  • Full-scale input voltage: 800mVPP-DIFF
  • Full-power input bandwidth: 6GHz
  • JESD204C Serial data interface:
    • Support for 2 to 8 total SerDes lanes
    • Maximum baud-rate: 17.16Gbps
    • 64B/66B and 8B/10B encoding modes
    • Subclass-1 support for deterministic latency
    • Compatible with JESD204B receivers
  • Optional internal sampling clock generation
    • Internal PLL and VCO (7.2–8.2GHz)
  • SYSREF Windowing eases synchronization
  • Four clock outputs simplify system clocking
    • Reference clocks for FPGA or adjacent ADC
    • Reference clock for SerDes transceivers
  • Timestamp input and output for pulsed systems
  • Power consumption (1 GSPS): 1.9W
  • Power supplies: 1.1V, 1.9V
  • Radiation Performance:
    • Total Ionizing Dose (TID): 300 krad (Si)
    • Single Event Latchup (SEL): 120 MeV-cm2/mg
    • Single Event Upset (SEU) immune registers
  • ADC Core:
    • Resolution: 12 Bit
    • Maximum sampling rate: 1.6GSPS
    • Non-interleaved architecture
    • Internal dither reduces high-order harmonics
  • Performance specifications (–1dBFS):
    • SNR (100 MHz): 57.4dBFS
    • ENOB (100 MHz): 9.1 Bits
    • SFDR (100 MHz): 64dBc
    • Noise floor (–20dBFS): –147dBFS
  • Full-scale input voltage: 800mVPP-DIFF
  • Full-power input bandwidth: 6GHz
  • JESD204C Serial data interface:
    • Support for 2 to 8 total SerDes lanes
    • Maximum baud-rate: 17.16Gbps
    • 64B/66B and 8B/10B encoding modes
    • Subclass-1 support for deterministic latency
    • Compatible with JESD204B receivers
  • Optional internal sampling clock generation
    • Internal PLL and VCO (7.2–8.2GHz)
  • SYSREF Windowing eases synchronization
  • Four clock outputs simplify system clocking
    • Reference clocks for FPGA or adjacent ADC
    • Reference clock for SerDes transceivers
  • Timestamp input and output for pulsed systems
  • Power consumption (1 GSPS): 1.9W
  • Power supplies: 1.1V, 1.9V

ADC12QJ1600-SP is a quad channel, 12-bit, 1.6GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the device suited for a variety of multi-channel communications systems.

Full-power input bandwidth (-3dB) of 6GHz enables direct RF sampling of L-band and S-band.

A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.

JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application.

ADC12QJ1600-SP is a quad channel, 12-bit, 1.6GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the device suited for a variety of multi-channel communications systems.

Full-power input bandwidth (-3dB) of 6GHz enables direct RF sampling of L-band and S-band.

A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.

JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application.
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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet ADC12QJ1600-SP Quad Channel 1.6GSPS, 12-Bit, Analog-to-Digital Converter (ADC) with JESD204C Interface datasheet (Rev. B) PDF | HTML Feb 19, 2025
* Radiation & reliability report ADC12QJ1600-SHP Production Flow and Reliability Report Mar 10, 2025
Application brief DLA Approved Optimizations for QML Products (Rev. C) PDF | HTML Jun 17, 2025
Technical article How SHP in plastic packaging addresses 3 key space application design challenges PDF | HTML Oct 17, 2022

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

ADC12QJ1600EVM — ADC12QJ1600 evaluation module for quad-channel, 12-bit, 1.6GSPS ADC with JESD204C interface

The ADC12QJ1600 evaluation module (EVM) is designed to evaluate the ADC12QJ1600-Q1 family of high-speed analog-to-digital converters (ADCs). The EVM is populated with the ADC12QJ1600-Q1, a 12-bit, quad-channel 1.6GSPS ADC with JESD204B interface and allows for evaluation of all sample rates and (...)
User guide: PDF
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Evaluation board

TSW12QJ1600EVM — ADC12QJ1600-Q1 8-ch (two synchronized 4-ch) 12-bit 1.6GSPS JESD204C interface ADC evaluation module

The TSW12QJ1600 evaluation module (EVM) is designed to evaluate the ADC12QJ1600-Q1 family of high-speed analog-to-digital converters (ADCs) with different front-end options. The EVM is populated with dual ADC12QJ1600-Q1, a 12-bit, quad-channel 1.6GSPS ADC with JESD204B interface and allows for (...)
User guide: PDF
Supported products & hardware
In stock
Limit:
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Simulation model

ADC09xJ800, ADC09xJ1300, ADC12xJ800 and ADC12xJ1600 IBIS-AMI Model (Rev. A)

SBAM512A.ZIP (22293 KB) - IBIS-AMI model
Supported products & hardware
Package Pins CAD symbols, footprints & 3D models
FCCSP (ALR) 144 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

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