ADC12xJ1600 is a family of quad, dual and single channel, 12-bit, 1.6GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the ADC12xJ1600 suited for a variety of multi-channel communications and test systems.
Full-power input bandwidth (−3dB) of 6GHz enables direct RF sampling of L-band and S-band.
A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.
JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | ADC12xJ1600 Quad, Dual, or Single Channel 1.6GSPS, 12-Bit, Analog-to-Digital Converter (ADC) with JESD204C Interface datasheet (Rev. A) | PDF | HTML | 06 Nov 2024 |
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The ADC12QJ1600 evaluation module (EVM) allows for the evaluation of the ADC12QJ1600-Q1 product. ADC12QJ1600-Q1 is a low-power, 12-bit, quad-channel, 1.6-GSPS analog-to-digital converter (ADC) with a buffered analog input and integrated digital down converter with on-chip PLL, which features a (...)
The TSW12QJ1600 evaluation module (EVM) is used to evaluate the ADC12QJ1600-Q1 analog-to-digital converter (ADC) with different front-end options. ADC12QJ1600-Q1 is a 12-bit ADC capable of operating at sampling rates up to 1.6 gigasample per second (GSPS) with four analog input channels.
This design (...)
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| FCCSP (AAV) | 144 | Ultra Librarian |
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