The ADC344x devices are a high-linearity, ultra-low power, quad-channel, 14-bit, 25-MSPS to 125-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock architecture design while the SYSREF input enables complete system synchronization.
The ADC344x family supports serial low-voltage differential signaling (LVDS) to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over two LVDS pairs. Optionally, a one-wire serial LVDS interface is available. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 14-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are transmitted as LVDS outputs.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | ADC344x Quad-Channel, 14-Bit, 25-MSPS to 125-MSPS, Analog-to-Digital Converters datasheet (Rev. B) | PDF | HTML | 17 Apr 2017 |
| EVM User's guide | ADC3xxxEVM and ADC3xJxxEVM User's Guide (Rev. D) | 24 Aug 2018 |
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The ADC3443 EVM demonstrates the performance of a low power quad 80Msps 14 bit ADC. It includes the ADC3443 device and TI voltage regulators to provide the necessary voltages. The input for the ADC is by default connected to the transformer input which can be connected to a 50 ohm (...)
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| VQFN (RTQ) | 56 | Ultra Librarian |
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