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High-speed ADCs (≥10 MSPS)

ADS4128

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12-Bit, 200-MSPS Analog-to-Digital Converter (ADC)

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Data sheet

ADS4128

ACTIVE
Data sheet Order now

Product details

Sample rate (max) (Msps) 200 Resolution (Bits) 12 Number of input channels 1 Interface type DDR LVDS, Parallel CMOS Analog input BW (MHz) 800 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 212 Architecture Pipeline SNR (dB) 70 ENOB (Bits) 11.2 SFDR (dB) 87 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 200 Resolution (Bits) 12 Number of input channels 1 Interface type DDR LVDS, Parallel CMOS Analog input BW (MHz) 800 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 212 Architecture Pipeline SNR (dB) 70 ENOB (Bits) 11.2 SFDR (dB) 87 Operating temperature range (°C) -40 to 85 Input buffer No
VQFN (RGZ) 48 49 mm² 7 x 7
  • Maximum Sample Rate: 200 MSPS
  • Ultralow Power with 1.8-V Single Supply:
    • 230-mW Total Power at 200 MSPS
  • High Dynamic Performance:
    • SNR: 69 dBFS at 170 MHz
    • SFDR: 85 dBc at 170 MHz
  • Dynamic Power Scaling With Sample Rate
  • Output Interface:
    • Double Data Rate (DDR) LVDS with
      Programmable Swing and Strength
      • Standard Swing: 350 mV
      • Low Swing: 200 mV
      • Default Strength: 100-Ω Termination
      • 2× Strength: 50-Ω Termination
    • 1.8-V Parallel CMOS Interface Also Supported
  • Programmable Gain up to 6 dB for SNR and

    SFDR Trade-Off
  • DC Offset Correction
  • Supports Low Input Clock Amplitude Down to 200
    mVPP
  • Package: 7.00 mm × 7.00 mm VQFN-48
  • Maximum Sample Rate: 200 MSPS
  • Ultralow Power with 1.8-V Single Supply:
    • 230-mW Total Power at 200 MSPS
  • High Dynamic Performance:
    • SNR: 69 dBFS at 170 MHz
    • SFDR: 85 dBc at 170 MHz
  • Dynamic Power Scaling With Sample Rate
  • Output Interface:
    • Double Data Rate (DDR) LVDS with
      Programmable Swing and Strength
      • Standard Swing: 350 mV
      • Low Swing: 200 mV
      • Default Strength: 100-Ω Termination
      • 2× Strength: 50-Ω Termination
    • 1.8-V Parallel CMOS Interface Also Supported
  • Programmable Gain up to 6 dB for SNR and

    SFDR Trade-Off
  • DC Offset Correction
  • Supports Low Input Clock Amplitude Down to 200
    mVPP
  • Package: 7.00 mm × 7.00 mm VQFN-48

The ADS4128 is a 12-bit analog-to-digital converter (ADC) with sampling rates up to 200 MSPS. This device uses innovative design techniques to achieve high dynamic performance, while consuming extremely low power at 1.8-V supply. The device is well-suited for multi-carrier, wide-bandwidth communications applications.

The ADS4128 has fine-gain options that can be used to improve SFDR performance at lower full-scale input ranges, especially at high input frequencies. It includes a dc offset correction loop that can be used to cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled-down power with no loss in performance.

The ADS4128 is available in a compact VQFN-48 package and is specified over the industrial temperature range (–40°C to 85°C).

The ADS4128 is a 12-bit analog-to-digital converter (ADC) with sampling rates up to 200 MSPS. This device uses innovative design techniques to achieve high dynamic performance, while consuming extremely low power at 1.8-V supply. The device is well-suited for multi-carrier, wide-bandwidth communications applications.

The ADS4128 has fine-gain options that can be used to improve SFDR performance at lower full-scale input ranges, especially at high input frequencies. It includes a dc offset correction loop that can be used to cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled-down power with no loss in performance.

The ADS4128 is available in a compact VQFN-48 package and is specified over the industrial temperature range (–40°C to 85°C).
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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet ADS4128 12-Bit, 200-MSPS, Ultralow-Power ADC datasheet (Rev. A) PDF | HTML 04 Apr 2016
Application note Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) 22 May 2015
Application note Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) 19 Jul 2013
User guide Interfacing Altera FPGAs to ADS4249 and DAC3482 (TIDA-00069 Reference Guide) 10 Jul 2012

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ADS4128 IBIS Model

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