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High-speed ADCs (≥10 MSPS)

ADS5413

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12-Bit, 65-MSPS, 1.0-GHz Input Bandwidth Analog-to-Digital Converter (ADC)

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Data sheet

ADS5413

ACTIVE
Data sheet Order now

Product details

Sample rate (max) (Msps) 65 Resolution (Bits) 12 Number of input channels 1 Interface type Parallel CMOS Analog input BW (MHz) 1000 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2.25 Power consumption (typ) (mW) 400 Architecture Pipeline SNR (dB) 68.5 ENOB (Bits) 11.3 SFDR (dB) 81 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 65 Resolution (Bits) 12 Number of input channels 1 Interface type Parallel CMOS Analog input BW (MHz) 1000 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2.25 Power consumption (typ) (mW) 400 Architecture Pipeline SNR (dB) 68.5 ENOB (Bits) 11.3 SFDR (dB) 81 Operating temperature range (°C) -40 to 85 Input buffer No
HTQFP (PHP) 48 81 mm² 9 x 9
  • 12-Bit Resolution
  • 65-MSPS Maximum Sample Rate
  • 2-Vpp Differential Input Range
  • 3.3-V Single Supply Operation
  • 1.8-V to 3.3-V Output Supply
  • 400-mW Total Power Dissipation
  • Two’s Complement Output Format
  • On-Chip S/H and Duty Cycle Adjust Circuit
  • Internal or External Reference
  • 48-Pin TQFP Package With PowerPad
    (7 mm x 7 mm body size)
  • 64.5-dBFS SNR and 72-dBc SFDR at 65 MSPS and 190-MHz Input
  • Power-Down Mode
  • Single-Ended or Differential Clock
  • 1-GHz -3-dB Input Bandwidth
  • APPLICATIONS
    • High IF Sampling Receivers
    • Medical Imaging
    • Portable Instrumentation

CommsADC is a trademark of Texas Instruments.
  • 12-Bit Resolution
  • 65-MSPS Maximum Sample Rate
  • 2-Vpp Differential Input Range
  • 3.3-V Single Supply Operation
  • 1.8-V to 3.3-V Output Supply
  • 400-mW Total Power Dissipation
  • Two’s Complement Output Format
  • On-Chip S/H and Duty Cycle Adjust Circuit
  • Internal or External Reference
  • 48-Pin TQFP Package With PowerPad
    (7 mm x 7 mm body size)
  • 64.5-dBFS SNR and 72-dBc SFDR at 65 MSPS and 190-MHz Input
  • Power-Down Mode
  • Single-Ended or Differential Clock
  • 1-GHz -3-dB Input Bandwidth
  • APPLICATIONS
    • High IF Sampling Receivers
    • Medical Imaging
    • Portable Instrumentation

CommsADC is a trademark of Texas Instruments.

The ADS5413 is a low power, 12-bit, 65-MSPS, CMOS pipeline analog-to-digital converter (ADC) that operates from a single 3.3-V supply, while offering the choice of digital output levels from 1.8 V to 3.3 V. The low noise, high linearity, and low clock jitter makes the ADC well suited for high-input frequency sampling applications. On-chip duty cycle adjust circuit allows the use of a non-50% duty cycle. This can be bypassed for applications requiring low jitter or asynchronous sampling. The device can also be clocked with single ended or differential clock, without change in performance. The internal reference can be bypassed to use an external reference to suit the accuracy and low drift requirements of the application.

The device is specified over full temperature range (–40°C to +85°C).

The ADS5413 is a low power, 12-bit, 65-MSPS, CMOS pipeline analog-to-digital converter (ADC) that operates from a single 3.3-V supply, while offering the choice of digital output levels from 1.8 V to 3.3 V. The low noise, high linearity, and low clock jitter makes the ADC well suited for high-input frequency sampling applications. On-chip duty cycle adjust circuit allows the use of a non-50% duty cycle. This can be bypassed for applications requiring low jitter or asynchronous sampling. The device can also be clocked with single ended or differential clock, without change in performance. The internal reference can be bypassed to use an external reference to suit the accuracy and low drift requirements of the application.

The device is specified over full temperature range (–40°C to +85°C).
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Top documentation Type Title Format options Date
* Data sheet ADS5413: 12-bit, 65 MSPS CommsADC Analog-to-Digital Converter datasheet 16 Dec 2003
Application note Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) 22 May 2015
Application note Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) 19 Jul 2013
Application note High-Speed, Analog-to-Digital Converter Basics 11 Jan 2012
Application note Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) 10 Sep 2010
Application note Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio 28 Apr 2009
Application note CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters 08 Jun 2008
Application note Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 02 Jun 2008
Application note Standard Procedure Direct Measurement Sub-picosecond RMS Jitter High-Speed ADC 30 Jun 2004
Application note How to Calculate the Period Jitter from the SSCR for High-Speed ADCs 17 Dec 2003

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