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High-speed ADCs (≥10 MSPS)

ADS62P19

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Dual-Channel, 11-Bit, 250-MSPS Analog-to-Digital Converter (ADC)

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Data sheet

ADS62P19

ACTIVE
Data sheet Order now

Product details

Sample rate (max) (Msps) 250 Resolution (Bits) 11 Number of input channels 2 Interface type DDR LVDS, Parallel CMOS Analog input BW (MHz) 700 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 1250 Architecture Pipeline SNR (dB) 66.5 ENOB (Bits) 10.6 SFDR (dB) 98 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 250 Resolution (Bits) 11 Number of input channels 2 Interface type DDR LVDS, Parallel CMOS Analog input BW (MHz) 700 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 1250 Architecture Pipeline SNR (dB) 66.5 ENOB (Bits) 10.6 SFDR (dB) 98 Operating temperature range (°C) -40 to 85 Input buffer No
VQFN (RGC) 64 81 mm² 9 x 9
  • Maximum Sample Rate: 250 MSPS
  • 11-Bit Resolution
  • Total Power: 1.25 W at 250 MSPS
  • Output Options:
    • DDR LVDS and Parallel CMOS
  • Programmable Gain:
    • Up to 6 dB for SNR and SFDR Trade-Off
  • DC Offset Correction
  • Crosstalk: 90 dB
  • Supports Input Clock Amplitude Down to
    400 mVPP, Differential
  • Internal and External Reference Support
  • Package: 9-mm × 9-mm QFN-64

All trademarks are the property of their respective owners.
  • Maximum Sample Rate: 250 MSPS
  • 11-Bit Resolution
  • Total Power: 1.25 W at 250 MSPS
  • Output Options:
    • DDR LVDS and Parallel CMOS
  • Programmable Gain:
    • Up to 6 dB for SNR and SFDR Trade-Off
  • DC Offset Correction
  • Crosstalk: 90 dB
  • Supports Input Clock Amplitude Down to
    400 mVPP, Differential
  • Internal and External Reference Support
  • Package: 9-mm × 9-mm QFN-64

All trademarks are the property of their respective owners.

The ADS62P19 is part of a family of dual-channel, 11-bit, analog-to-digital converters (ADCs) with sampling rates up to 250 MSPS. The device combines high dynamic performance and low power consumption in a compact QFN-64 package. This functionality makes the device well-suited for multi-carrier, wide-bandwidth communication applications.

The ADS62P19 has gain options that can be used to improve spurious-free dynamic range (SFDR) performance at lower full-scale input ranges. The device includes a dc offset correction loop that can be used to cancel ADC offset. Both double data rate (DDR) low-voltage differential signaling (LVDS) and parallel complementary metal oxide semiconductor (CMOS) digital output interfaces are available.

Although the device includes internal references, the traditional reference pins and associated decoupling capacitors are eliminated. Nevertheless, the device can also be driven with an external reference. The device is specified over the industrial temperature range (–40°C to +85°C).

The ADS62P19 is part of a family of dual-channel, 11-bit, analog-to-digital converters (ADCs) with sampling rates up to 250 MSPS. The device combines high dynamic performance and low power consumption in a compact QFN-64 package. This functionality makes the device well-suited for multi-carrier, wide-bandwidth communication applications.

The ADS62P19 has gain options that can be used to improve spurious-free dynamic range (SFDR) performance at lower full-scale input ranges. The device includes a dc offset correction loop that can be used to cancel ADC offset. Both double data rate (DDR) low-voltage differential signaling (LVDS) and parallel complementary metal oxide semiconductor (CMOS) digital output interfaces are available.

Although the device includes internal references, the traditional reference pins and associated decoupling capacitors are eliminated. Nevertheless, the device can also be driven with an external reference. The device is specified over the industrial temperature range (–40°C to +85°C).
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* Data sheet Dual-Channel, 11-Bit, 250-MSPS ADC With DDR LVDS and Parallel CMOS Outputs datasheet 30 Apr 2013
Application note Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) 22 May 2015
Application note Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) 19 Jul 2013

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