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AMIC120

ACTIVE

Sitara processor; Arm Cortex-A9; 10+ Ethernet protocols, encoder protocols

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AMIC120

ACTIVE
Data sheet Order now

Product details

CPU 1 Arm Cortex-A9 Frequency (MHz) 300 Protocols EtherCAT, EtherNet/IP, Ethernet, Profibus, Profinet, Sercos Hardware accelerators Industrial communications subsystem, Programable real-time unit, Security Accelerator Features Networking Security Cryptographic acceleration Rating Catalog Power supply solution TPS650250, TPS65216 Operating temperature range (°C) -40 to 105
CPU 1 Arm Cortex-A9 Frequency (MHz) 300 Protocols EtherCAT, EtherNet/IP, Ethernet, Profibus, Profinet, Sercos Hardware accelerators Industrial communications subsystem, Programable real-time unit, Security Accelerator Features Networking Security Cryptographic acceleration Rating Catalog Power supply solution TPS650250, TPS65216 Operating temperature range (°C) -40 to 105
NFBGA (ZDN) 491 289 mm² 17 x 17
  • Highlights
    • Sitara™ ARM® Cortex®-A9 32-Bit RISC Processor With Processing Speed up to 300 MHz
      • NEON™ SIMD Coprocessor and Vector Floating Point (VFPv3) Coprocessor
      • 32KB of Both L1 Instruction and Data Cache
      • 256KB of L2 Cache or L3 RAM
    • 32-Bit LPDDR2, DDR3, and DDR3L Support
    • General-Purpose Memory Support (NAND, NOR, SRAM) Supporting up to 16-Bit ECC
    • Real-Time Clock (RTC)
    • Up to Two USB 2.0 High-Speed Dual-Role (Host or Device) Ports With Integrated PHY
    • 10, 100, and 1000 Ethernet Switch Supporting up to Two Ports (Only 1 Port is Pinned out on this Device)
    • Serial Interfaces:
      • Six UARTs, Two McASPs, Five McSPIs, Three I2C Ports, One QSPI, and One HDQ or 1-Wire
    • Security
      • Crypto Hardware Accelerators (AES, SHA, RNG, DES, and 3DES)
    • Two 12-Bit Successive Approximation Register (SAR) ADCs
    • Up to Three 32-Bit Enhanced Capture (eCAP) Modules
    • Up to Three Enhanced Quadrature Encoder Pulse (eQEP) Modules
    • Up to Six Enhanced High-Resolution PWM (eHRPWM) Modules
  • MPU Subsystem
    • ARM Cortex-A9 32-Bit RISC Microprocessor With Processing Speed up to 300 MHz
    • 32KB of Both L1 Instruction and Data Cache
    • 256KB of L2 Cache (Option to Configure as L3 RAM)
    • 256KB of On-Chip Boot ROM
    • 64KB of On-Chip RAM
    • Emulation and Debug
      • JTAG
      • Embedded Trace Buffer
    • Interrupt Controller
  • On-Chip Memory (Shared L3 RAM)
    • 256KB of General-Purpose On-Chip Memory Controller (OCMC) RAM
    • Accessible to All Masters
    • Supports Retention for Fast Wakeup
    • Up to 512KB of Total Internal RAM
      (256KB of ARM Memory Configured as L3 RAM + 256KB of OCMC RAM)
  • External Memory Interfaces (EMIFs)
    • DDR Controllers:
      • LPDDR2: 266-MHz Clock (LPDDR2-533 Data Rate)
      • DDR3 and DDR3L: 400-MHz Clock (DDR-800 Data Rate)
      • 32-Bit Data Bus
      • 2GB of Total Addressable Space
      • Supports One x32, Two x16, or Four x8 Memory Device Configurations
  • General-Purpose Memory Controller (GPMC)
    • Flexible 8- and 16-Bit Asynchronous Memory Interface With up to Seven Chip Selects (NAND, NOR, Muxed-NOR, and SRAM)
    • Uses BCH Code to Support 4-, 8-, or 16-Bit ECC
    • Uses Hamming Code to Support 1-Bit ECC
  • Error Locator Module (ELM)
    • Used With the GPMC to Locate Addresses of Data Errors From Syndrome Polynomials Generated Using a BCH Algorithm
    • Supports 4-, 8-, and 16-Bit Per 512-Byte Block Error Location Based on BCH Algorithms
  • Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
    • Supports Protocols such as EtherCAT®, PROFIBUS®, PROFINET®, and EtherNet/IP™, EnDat 2.2, and More
    • Two Programmable Real-Time Units (PRUs) Subsystems With Two PRU Cores Each
      • Each Core is a 32-Bit Load and Store RISC Processor Capable of Running at 200 MHz
      • 12KB (PRU-ICSS1), 4KB (PRU-ICSS0) of Instruction RAM With Single-Error Detection (Parity)
      • 8KB (PRU-ICSS1), 4KB (PRU-ICSS0) of Data RAM With Single-Error Detection (Parity)
      • Single-Cycle 32-Bit Multiplier With 64-Bit Accumulator
      • Enhanced GPIO Module Provides Shift-In and Shift-Out Support and Parallel Latch on External Signal
    • 12KB (PRU-ICSS1 Only) of Shared RAM With Single-Error Detection (Parity)
    • Three 120-Byte Register Banks Accessible by Each PRU
    • Interrupt Controller Module (INTC) for Handling System Input Events
    • Local Interconnect Bus for Connecting Internal and External Masters to the Resources Inside the PRU-ICSS
    • Peripherals Inside the PRU-ICSS
      • One UART Port With Flow Control Pins, Supports up to 12 Mbps
      • One eCAP Module
      • Two MII Ethernet Ports that Support Industrial Ethernet, such as EtherCAT
      • One MDIO Port
    • Industrial Communication is Supported by Two PRU-ICSS Subsystems
  • Power, Reset, and Clock Management (PRCM) Module
    • Controls the Entry and Exit of Deep-Sleep Modes
    • Responsible for Sleep Sequencing, Power Domain Switch-Off Sequencing, Wake-Up Sequencing, and Power Domain Switch-On Sequencing
    • Clocks
      • Integrated High-Frequency Oscillator Used to Generate a Reference Clock (19.2, 24, 25, and 26 MHz) for Various System and Peripheral Clocks
      • Supports Individual Clock Enable and Disable Control for Subsystems and Peripherals to Facilitate Reduced Power Consumption
      • Five ADPLLs to Generate System Clocks (MPU Subsystem, DDR Interface, USB, and Peripherals [MMC and SD, UART, SPI, I2C], L3, L4, and Ethernet)
    • Power
      • Two Nonswitchable Power Domains (RTC and Wake-Up Logic [WAKE-UP])
      • Two Switchable Power Domains (MPU Subsystem, Peripherals and Infrastructure [PER])
      • Dynamic Voltage Frequency Scaling (DVFS)
  • Real-Time Clock (RTC)
    • Real-Time Date (Day, Month, Year, and Day of Week) and Time (Hours, Minutes, and Seconds) Information
    • Internal 32.768-kHz Oscillator, RTC Logic, and 1.1-V Internal LDO
    • Independent Power-On-Reset (RTC_PWRONRSTn) Input
    • Dedicated Input Pin (RTC_WAKEUP) for External Wake Events
    • Programmable Alarm Can Generate Internal Interrupts to the PRCM for Wakeup or Cortex-A9 for Event Notification
    • Programmable Alarm Can Be Used With External Output (RTC_PMIC_EN) to Enable the Power-Management IC to Restore Non-RTC Power Domains
  • Peripherals
    • Up to Two USB 2.0 High-Speed Dual-Role (Host or Device) Ports With Integrated PHY
    • Up to Two Industrial Gigabit Ethernet MACs
      (10, 100, and 1000 Mbps)
      • Integrated Switch
      • MAC Supports MII, RMII, and RGMII and MDIO Interfaces
      • Ethernet MAC and Switch Can Operate Independent of Other Functions
      • IEEE 1588v2 Precision Time Protocol (PTP)
    • Up to Two CAN Ports
      • Supports CAN Version 2 Parts A and B
    • Up to Two Multichannel Audio Serial Ports (McASPs)
      • Transmit and Receive Clocks up to 50 MHz
      • Up to Four Serial Data Pins Per McASP Port With Independent TX and RX Clocks
      • Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats
      • Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
      • FIFO Buffers for Transmit and Receive (256 Bytes)
    • Up to Six UARTs
      • All UARTs Support IrDA and CIR Modes
      • All UARTs Support RTS and CTS Flow Control
      • UART1 Supports Full Modem Control
    • Up to Five Master and Slave McSPIs
      • McSPI0–McSPI2 Support up to Four Chip Selects
      • McSPI3 and McSPI4 Support up to Two Chip Selects
      • Up to 48 MHz
    • One Quad-SPI
      • Supports eXecute In Place (XIP) from Serial NOR FLASH
    • One Dallas 1-Wire® and HDQ Serial Interface
    • Up to Three MMC, SD, and SDIO Ports
      • 1-, 4-, and 8-Bit MMC, SD, and SDIO Modes
      • 1.8- or 3.3-V Operation on All Ports
      • Up to 48-MHz Clock
      • Supports Card Detect and Write Protect
      • Complies With MMC4.3 and SD and SDIO 2.0 Specifications
    • Up to Three I2C Master and Slave Interfaces
      • Standard Mode (up to 100 kHz)
      • Fast Mode (up to 400 kHz)
    • Up to Six Banks of General-Purpose I/O (GPIO)
      • 32 GPIOs per Bank (Multiplexed With Other Functional Pins)
      • GPIOs Can be Used as Interrupt Inputs (up to Two Interrupt Inputs per Bank)
    • Up to Three External DMA Event Inputs That Can Also be Used as Interrupt Inputs
    • Twelve 32-Bit General-Purpose Timers
      • DMTIMER1 is a 1-ms Timer Used for Operating System (OS) Ticks
      • DMTIMER4–DMTIMER7 are Pinned Out
    • One Public Watchdog Timer
    • One Free-Running, High-Resolution 32-kHz Counter (synctimer32K)
    • Two 12-Bit SAR ADCs (ADC0, ADC1)
      • 867K Samples Per Second
      • Input Can Be Selected from Any of the Eight Analog Inputs Multiplexed Through an 8:1 Analog Switch
    • Up to Three 32-Bit eCAP Modules
      • Configurable as Three Capture Inputs or Three Auxiliary PWM Outputs
    • Up to Six Enhanced eHRPWM Modules
      • Dedicated 16-Bit Time-Base Counter With Time and Frequency Controls
      • Configurable as Six Single-Ended, Six Dual-Edge Symmetric, or Three Dual-Edge Asymmetric Outputs
    • Up to Three 32-Bit eQEP Modules
  • Device Identification
    • Factory Programmable Electrical Fuse Farm (FuseFarm)
      • Production ID
      • Device Part Number (Unique JTAG ID)
      • Device Revision (Readable by Host ARM)
  • Debug Interface Support
    • JTAG and cJTAG for ARM (Cortex-A9 and PRCM) and PRU-ICSS Debug
    • Supports Real-Time Trace Pins (for Cortex-A9)
    • 64-KB Embedded Trace Buffer (ETB)
    • Supports Device Boundary Scan
    • Supports IEEE 1500
  • DMA
    • On-Chip Enhanced DMA Controller (EDMA) Has Three Third-Party Transfer Controllers (TPTCs) and One Third-Party Channel Controller (TPCC), Which Supports up to 64 Programmable Logical Channels and Eight QDMA Channels
    • EDMA is Used for:
      • Transfers to and from On-Chip Memories
      • Transfers to and from External Storage (EMIF, GPMC, and Slave Peripherals)
  • InterProcessor Communication (IPC)
    • Integrates Hardware-Based Mailbox for IPC and Spinlock for Process Synchronization Between the Cortex-A9, PRCM, and PRU-ICSS
  • Boot Modes
    • Boot Mode is Selected Through Boot Configuration Pins Latched on the Rising Edge of the PWRONRSTn Reset Input Pin
  • Package
    • 491-Pin BGA Package (17-mm × 17-mm) (ZDN Suffix), 0.65-mm Ball Pitch With Via Channel Array Technology to Enable Low-Cost Routing
  • Highlights
    • Sitara™ ARM® Cortex®-A9 32-Bit RISC Processor With Processing Speed up to 300 MHz
      • NEON™ SIMD Coprocessor and Vector Floating Point (VFPv3) Coprocessor
      • 32KB of Both L1 Instruction and Data Cache
      • 256KB of L2 Cache or L3 RAM
    • 32-Bit LPDDR2, DDR3, and DDR3L Support
    • General-Purpose Memory Support (NAND, NOR, SRAM) Supporting up to 16-Bit ECC
    • Real-Time Clock (RTC)
    • Up to Two USB 2.0 High-Speed Dual-Role (Host or Device) Ports With Integrated PHY
    • 10, 100, and 1000 Ethernet Switch Supporting up to Two Ports (Only 1 Port is Pinned out on this Device)
    • Serial Interfaces:
      • Six UARTs, Two McASPs, Five McSPIs, Three I2C Ports, One QSPI, and One HDQ or 1-Wire
    • Security
      • Crypto Hardware Accelerators (AES, SHA, RNG, DES, and 3DES)
    • Two 12-Bit Successive Approximation Register (SAR) ADCs
    • Up to Three 32-Bit Enhanced Capture (eCAP) Modules
    • Up to Three Enhanced Quadrature Encoder Pulse (eQEP) Modules
    • Up to Six Enhanced High-Resolution PWM (eHRPWM) Modules
  • MPU Subsystem
    • ARM Cortex-A9 32-Bit RISC Microprocessor With Processing Speed up to 300 MHz
    • 32KB of Both L1 Instruction and Data Cache
    • 256KB of L2 Cache (Option to Configure as L3 RAM)
    • 256KB of On-Chip Boot ROM
    • 64KB of On-Chip RAM
    • Emulation and Debug
      • JTAG
      • Embedded Trace Buffer
    • Interrupt Controller
  • On-Chip Memory (Shared L3 RAM)
    • 256KB of General-Purpose On-Chip Memory Controller (OCMC) RAM
    • Accessible to All Masters
    • Supports Retention for Fast Wakeup
    • Up to 512KB of Total Internal RAM
      (256KB of ARM Memory Configured as L3 RAM + 256KB of OCMC RAM)
  • External Memory Interfaces (EMIFs)
    • DDR Controllers:
      • LPDDR2: 266-MHz Clock (LPDDR2-533 Data Rate)
      • DDR3 and DDR3L: 400-MHz Clock (DDR-800 Data Rate)
      • 32-Bit Data Bus
      • 2GB of Total Addressable Space
      • Supports One x32, Two x16, or Four x8 Memory Device Configurations
  • General-Purpose Memory Controller (GPMC)
    • Flexible 8- and 16-Bit Asynchronous Memory Interface With up to Seven Chip Selects (NAND, NOR, Muxed-NOR, and SRAM)
    • Uses BCH Code to Support 4-, 8-, or 16-Bit ECC
    • Uses Hamming Code to Support 1-Bit ECC
  • Error Locator Module (ELM)
    • Used With the GPMC to Locate Addresses of Data Errors From Syndrome Polynomials Generated Using a BCH Algorithm
    • Supports 4-, 8-, and 16-Bit Per 512-Byte Block Error Location Based on BCH Algorithms
  • Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
    • Supports Protocols such as EtherCAT®, PROFIBUS®, PROFINET®, and EtherNet/IP™, EnDat 2.2, and More
    • Two Programmable Real-Time Units (PRUs) Subsystems With Two PRU Cores Each
      • Each Core is a 32-Bit Load and Store RISC Processor Capable of Running at 200 MHz
      • 12KB (PRU-ICSS1), 4KB (PRU-ICSS0) of Instruction RAM With Single-Error Detection (Parity)
      • 8KB (PRU-ICSS1), 4KB (PRU-ICSS0) of Data RAM With Single-Error Detection (Parity)
      • Single-Cycle 32-Bit Multiplier With 64-Bit Accumulator
      • Enhanced GPIO Module Provides Shift-In and Shift-Out Support and Parallel Latch on External Signal
    • 12KB (PRU-ICSS1 Only) of Shared RAM With Single-Error Detection (Parity)
    • Three 120-Byte Register Banks Accessible by Each PRU
    • Interrupt Controller Module (INTC) for Handling System Input Events
    • Local Interconnect Bus for Connecting Internal and External Masters to the Resources Inside the PRU-ICSS
    • Peripherals Inside the PRU-ICSS
      • One UART Port With Flow Control Pins, Supports up to 12 Mbps
      • One eCAP Module
      • Two MII Ethernet Ports that Support Industrial Ethernet, such as EtherCAT
      • One MDIO Port
    • Industrial Communication is Supported by Two PRU-ICSS Subsystems
  • Power, Reset, and Clock Management (PRCM) Module
    • Controls the Entry and Exit of Deep-Sleep Modes
    • Responsible for Sleep Sequencing, Power Domain Switch-Off Sequencing, Wake-Up Sequencing, and Power Domain Switch-On Sequencing
    • Clocks
      • Integrated High-Frequency Oscillator Used to Generate a Reference Clock (19.2, 24, 25, and 26 MHz) for Various System and Peripheral Clocks
      • Supports Individual Clock Enable and Disable Control for Subsystems and Peripherals to Facilitate Reduced Power Consumption
      • Five ADPLLs to Generate System Clocks (MPU Subsystem, DDR Interface, USB, and Peripherals [MMC and SD, UART, SPI, I2C], L3, L4, and Ethernet)
    • Power
      • Two Nonswitchable Power Domains (RTC and Wake-Up Logic [WAKE-UP])
      • Two Switchable Power Domains (MPU Subsystem, Peripherals and Infrastructure [PER])
      • Dynamic Voltage Frequency Scaling (DVFS)
  • Real-Time Clock (RTC)
    • Real-Time Date (Day, Month, Year, and Day of Week) and Time (Hours, Minutes, and Seconds) Information
    • Internal 32.768-kHz Oscillator, RTC Logic, and 1.1-V Internal LDO
    • Independent Power-On-Reset (RTC_PWRONRSTn) Input
    • Dedicated Input Pin (RTC_WAKEUP) for External Wake Events
    • Programmable Alarm Can Generate Internal Interrupts to the PRCM for Wakeup or Cortex-A9 for Event Notification
    • Programmable Alarm Can Be Used With External Output (RTC_PMIC_EN) to Enable the Power-Management IC to Restore Non-RTC Power Domains
  • Peripherals
    • Up to Two USB 2.0 High-Speed Dual-Role (Host or Device) Ports With Integrated PHY
    • Up to Two Industrial Gigabit Ethernet MACs
      (10, 100, and 1000 Mbps)
      • Integrated Switch
      • MAC Supports MII, RMII, and RGMII and MDIO Interfaces
      • Ethernet MAC and Switch Can Operate Independent of Other Functions
      • IEEE 1588v2 Precision Time Protocol (PTP)
    • Up to Two CAN Ports
      • Supports CAN Version 2 Parts A and B
    • Up to Two Multichannel Audio Serial Ports (McASPs)
      • Transmit and Receive Clocks up to 50 MHz
      • Up to Four Serial Data Pins Per McASP Port With Independent TX and RX Clocks
      • Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats
      • Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
      • FIFO Buffers for Transmit and Receive (256 Bytes)
    • Up to Six UARTs
      • All UARTs Support IrDA and CIR Modes
      • All UARTs Support RTS and CTS Flow Control
      • UART1 Supports Full Modem Control
    • Up to Five Master and Slave McSPIs
      • McSPI0–McSPI2 Support up to Four Chip Selects
      • McSPI3 and McSPI4 Support up to Two Chip Selects
      • Up to 48 MHz
    • One Quad-SPI
      • Supports eXecute In Place (XIP) from Serial NOR FLASH
    • One Dallas 1-Wire® and HDQ Serial Interface
    • Up to Three MMC, SD, and SDIO Ports
      • 1-, 4-, and 8-Bit MMC, SD, and SDIO Modes
      • 1.8- or 3.3-V Operation on All Ports
      • Up to 48-MHz Clock
      • Supports Card Detect and Write Protect
      • Complies With MMC4.3 and SD and SDIO 2.0 Specifications
    • Up to Three I2C Master and Slave Interfaces
      • Standard Mode (up to 100 kHz)
      • Fast Mode (up to 400 kHz)
    • Up to Six Banks of General-Purpose I/O (GPIO)
      • 32 GPIOs per Bank (Multiplexed With Other Functional Pins)
      • GPIOs Can be Used as Interrupt Inputs (up to Two Interrupt Inputs per Bank)
    • Up to Three External DMA Event Inputs That Can Also be Used as Interrupt Inputs
    • Twelve 32-Bit General-Purpose Timers
      • DMTIMER1 is a 1-ms Timer Used for Operating System (OS) Ticks
      • DMTIMER4–DMTIMER7 are Pinned Out
    • One Public Watchdog Timer
    • One Free-Running, High-Resolution 32-kHz Counter (synctimer32K)
    • Two 12-Bit SAR ADCs (ADC0, ADC1)
      • 867K Samples Per Second
      • Input Can Be Selected from Any of the Eight Analog Inputs Multiplexed Through an 8:1 Analog Switch
    • Up to Three 32-Bit eCAP Modules
      • Configurable as Three Capture Inputs or Three Auxiliary PWM Outputs
    • Up to Six Enhanced eHRPWM Modules
      • Dedicated 16-Bit Time-Base Counter With Time and Frequency Controls
      • Configurable as Six Single-Ended, Six Dual-Edge Symmetric, or Three Dual-Edge Asymmetric Outputs
    • Up to Three 32-Bit eQEP Modules
  • Device Identification
    • Factory Programmable Electrical Fuse Farm (FuseFarm)
      • Production ID
      • Device Part Number (Unique JTAG ID)
      • Device Revision (Readable by Host ARM)
  • Debug Interface Support
    • JTAG and cJTAG for ARM (Cortex-A9 and PRCM) and PRU-ICSS Debug
    • Supports Real-Time Trace Pins (for Cortex-A9)
    • 64-KB Embedded Trace Buffer (ETB)
    • Supports Device Boundary Scan
    • Supports IEEE 1500
  • DMA
    • On-Chip Enhanced DMA Controller (EDMA) Has Three Third-Party Transfer Controllers (TPTCs) and One Third-Party Channel Controller (TPCC), Which Supports up to 64 Programmable Logical Channels and Eight QDMA Channels
    • EDMA is Used for:
      • Transfers to and from On-Chip Memories
      • Transfers to and from External Storage (EMIF, GPMC, and Slave Peripherals)
  • InterProcessor Communication (IPC)
    • Integrates Hardware-Based Mailbox for IPC and Spinlock for Process Synchronization Between the Cortex-A9, PRCM, and PRU-ICSS
  • Boot Modes
    • Boot Mode is Selected Through Boot Configuration Pins Latched on the Rising Edge of the PWRONRSTn Reset Input Pin
  • Package
    • 491-Pin BGA Package (17-mm × 17-mm) (ZDN Suffix), 0.65-mm Ball Pitch With Via Channel Array Technology to Enable Low-Cost Routing

The TI AMIC120 high-performance processors are based on the ARM Cortex-A9 core.

The processors are enhanced with a coprocessor for deterministic, real-time processing including industrial communication protocols, such as EtherCAT, PROFIBUS, EnDat, and others. The devices support high-level operating systems (HLOS). Linux® is available free of charge from TI. Other HLOSs are available from TI’s Design Network and ecosystem partners.

These devices offer an upgrade to systems based on lower performance ARM cores and provide updated peripherals, including memory options such as QSPI-NOR and LPDDR2.

The processors contain the subsystems shown in the Functional Block Diagram, and a brief description of each follows.

The programmable real-time unit subsystem and industrial communication subsystem (PRU-ICSS) is separate from the ARM core and allows independent operation and clocking for greater efficiency and flexibility. The PRU-ICSS enables additional peripheral interfaces and real-time protocols such as EtherCAT, PROFINET, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos, EnDat, and others. The PRU-ICSS enables EnDat and another industrial communication protocol in parallel. Additionally, the programmable nature of the PRU-ICSS, along with their access to pins, events and all system-on-chip (SoC) resources, provides flexibility in implementing fast real-time responses, specialized data handling operations, custom peripheral interfaces, and in off-loading tasks from the other processor cores of the SoC.

High-performance interconnects provide high-bandwidth data transfers for multiple initiators to the internal and external memory controllers and to on-chip peripherals. The device also offers a comprehensive clock-management scheme.

One on-chip analog to digital converter (ADC1) can combine with the pulse width module to create a closed-loop motor control solution.

The RTC provides a clock reference on a separate power domain. The clock reference enables a battery-backed clock reference.

Cryptographic acceleration is available in every AMIC120 device.

The TI AMIC120 high-performance processors are based on the ARM Cortex-A9 core.

The processors are enhanced with a coprocessor for deterministic, real-time processing including industrial communication protocols, such as EtherCAT, PROFIBUS, EnDat, and others. The devices support high-level operating systems (HLOS). Linux® is available free of charge from TI. Other HLOSs are available from TI’s Design Network and ecosystem partners.

These devices offer an upgrade to systems based on lower performance ARM cores and provide updated peripherals, including memory options such as QSPI-NOR and LPDDR2.

The processors contain the subsystems shown in the Functional Block Diagram, and a brief description of each follows.

The programmable real-time unit subsystem and industrial communication subsystem (PRU-ICSS) is separate from the ARM core and allows independent operation and clocking for greater efficiency and flexibility. The PRU-ICSS enables additional peripheral interfaces and real-time protocols such as EtherCAT, PROFINET, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos, EnDat, and others. The PRU-ICSS enables EnDat and another industrial communication protocol in parallel. Additionally, the programmable nature of the PRU-ICSS, along with their access to pins, events and all system-on-chip (SoC) resources, provides flexibility in implementing fast real-time responses, specialized data handling operations, custom peripheral interfaces, and in off-loading tasks from the other processor cores of the SoC.

High-performance interconnects provide high-bandwidth data transfers for multiple initiators to the internal and external memory controllers and to on-chip peripherals. The device also offers a comprehensive clock-management scheme.

One on-chip analog to digital converter (ADC1) can combine with the pulse width module to create a closed-loop motor control solution.

The RTC provides a clock reference on a separate power domain. The clock reference enables a battery-backed clock reference.

Cryptographic acceleration is available in every AMIC120 device.
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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet AMIC120 Sitara™ Processors datasheet (Rev. B) PDF | HTML 21 Mar 2018
* Errata AMIC120 Sitara Processors Silicon Errata 25 Apr 2017
* E-book E-book: An engineer’s guide to industrial robot designs 16 Nov 2020
Application note Industrial Communication Protocols Supported on TI Processors and MCUs (Rev. F) PDF | HTML 03 Sep 2025
White paper Industry 4.0 서보 드라이브에 Sitara™ 프로세서 및 마이크로컨트롤러 활용 (Rev. C) PDF | HTML 12 Jan 2022
White paper 運用適合工業 4.0 Sitara™ 伺服驅動器的處理器與微控制器 (Rev. C) PDF | HTML 12 Jan 2022
White paper Utilizing Sitara Processors and Microcontrollers for Industry 4.0 Servo Drives (Rev. C) 06 Oct 2021
Application note AM437x Schematic Checklist (Rev. A) 25 Sep 2020
White paper EtherCAT® on Sitara™ Processors (Rev. I) 28 Jul 2020
White paper EtherNet/IP on TI's Sitara AM335x Processors (Rev. D) 28 Jul 2020
E-book Ein Techniker-Leitfaden für Industrieroboter-Designs 25 Mar 2020
User guide AM437x and AMIC120 ARM® Cortex™-A9 Processors Technical Reference Manual (Rev. I) 23 Dec 2019
User guide Powering AMIC110, AMIC120, AM335x, and AM437x with TPS65216 11 Apr 2019
Application brief Flexible Timing Configuration with IO-Link Master Frame Handler 26 Mar 2019
Application note PRU-ICSS EtherCAT Slave Troubleshooting Guide 07 Nov 2018
White paper PROFINET on TI’s Sitara™ processors (Rev. D) 13 Oct 2018
User guide How-To and Troubleshooting Guide for PRU-ICSS PROFIBUS 24 Sep 2018
White paper Highly integrated single-chip industrial drive to connect, control & communicate 29 Apr 2015

Design & development

Power-supply solutions

Find available power-supply solutions for the AMIC120. TI offers power-supply solutions for TI and non-TI systems on a chip (SoCs), processors, microcontrollers, sensors, and field-programmable gate arrays (FPGAs).

View solutions
Evaluation board

TMDSIDK437X — AM437x/AMIC120 Industrial Development Kit (IDK)

The AM437x/AMIC120 Industrial Development Kit (IDK) is an application development platform for evaluating the industrial communication and control capabilities of Sitara™ AM4379, AM4377 and AMIC120 processors for industrial applications.

The  AM4379, AM4377 and AMIC120 processors are ideal for (...)

User guide: PDF
Not available on TI.com
Software development kit (SDK)

PROCESSOR-SDK-AMIC120 — Processor SDK for AMIC120 Sitara™ Processors – TI-RTOS Support

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos.  All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)
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Software development kit (SDK)

PROCESSOR-SDK-RTOS-AM437X — TI-RTOS processor SDK for AM437x and AMIC120 (No design support from TI available. Refer to Overview- RTOS Highlights for details.)

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos.  All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)

Supported products & hardware

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Driver or library

PRU-ICSS-ETHERCAT-SLAVE — PRU-ICSS software for EtherCAT slave

The PRU-ICSS Protocols enables real-time industrial communications for TI Sitara processors.  The PRU-ICSS protocols are built to use on top of Processor-SDK-RTOS, TI’s unified software development platform, and contain optimized PRU-ICSS firmware, a corresponding PRU-ICSS driver for the (...)

Supported products & hardware

Supported products & hardware
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IDE, configuration, compiler or debugger

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It is comprised of a rich suite of tools used to build, debug, analyze and optimize embedded applications. Code Composer Studio is available across Windows®, Linux® and macOS® platforms.

(...)

Supported products & hardware

Supported products & hardware
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IDE, configuration, compiler or debugger

SYSCONFIG — Standalone desktop version of SysConfig

SysConfig is a configuration tool designed to simplify hardware and software configuration challenges to accelerate software development.

SysConfig is available as part of the Code Composer Studio™ integrated development environment as well as a standalone application. Additionally SysConfig (...)

Supported products & hardware

Supported products & hardware
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Support software

AUTOMATA-3P-INDUSTRIALCOMMS — Cannon Automata Sercos III

The Sercos III Slave Communiction Stack allows to implement the Real-time Ethernet protocol Sercos III for any kind of slave devices. The source code includes SCP (Sercos Communication Profile) and GDP (General Device Profile). In addition, the stack already includes many optional function classes (...)
From: AUTOMATA
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Calculation tool

CLOCKTREETOOL — Clock Tree Tool for Sitara, Automotive, Vision Analytics, & Digital Signal Processors


The Clock Tree Tool (CTT) for ARM Processors & Digital Signal Processors is an interactive configuration software tool that provides information about device clock tree architecture. This tool allows visualization of the device clock tree. It can also be used to determine the exact register (...)
User guide: PDF
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Calculation tool

POWEREST — Power Estimation Tool (PET)

Power Estimation Tool (PET) provides users the ability to gain insight in to the power consumption of select TI processors. The tool includes the ability for the user to choose multiple application scenarios and understand the power consumption as well as how advanced power saving techniques can be (...)
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Package Pins CAD symbols, footprints & 3D models
NFBGA (ZDN) 491 Ultra Librarian
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