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CD74ACT175

ACTIVE

Quad D-Type Flip-Flops with Reset

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Data sheet

CD74ACT175

ACTIVE
Data sheet Order now

Product details

Number of channels 4 Technology family ACT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type TTL-Compatible CMOS Output type Push-Pull Clock frequency (max) (MHz) 114 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (µA) 80 Features Balanced outputs, Positive input clamp diode, Very high speed (tpd 5-10ns) Operating temperature range (°C) -55 to 125 Rating Catalog
Number of channels 4 Technology family ACT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type TTL-Compatible CMOS Output type Push-Pull Clock frequency (max) (MHz) 114 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (µA) 80 Features Balanced outputs, Positive input clamp diode, Very high speed (tpd 5-10ns) Operating temperature range (°C) -55 to 125 Rating Catalog
PDIP (N) 16 181.42 mm² 19.3 x 9.4 SOIC (D) 16 59.4 mm² 9.9 x 6
  • Inputs are TTL-voltage compatible
  • Contains four flip-flops with double-rail outputs
  • Buffered inputs
  • Speed of bipolar F, AS, and S, with significantly reduced power consumption
  • Balanced propagation delays
  • ±24mA output drive current
    • Fanout to 15 F devices
  • SCR-latchup-resistant CMOS process and circuit design
  • Inputs are TTL-voltage compatible
  • Contains four flip-flops with double-rail outputs
  • Buffered inputs
  • Speed of bipolar F, AS, and S, with significantly reduced power consumption
  • Balanced propagation delays
  • ±24mA output drive current
    • Fanout to 15 F devices
  • SCR-latchup-resistant CMOS process and circuit design

This positive-edge-triggered D-type flip-flop has a direct clear (CLR) input. The CD74ACT175 features complementary outputs from each flip-flop.

This positive-edge-triggered D-type flip-flop has a direct clear (CLR) input. The CD74ACT175 features complementary outputs from each flip-flop.
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Technical documentation

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Type Title Date
* Data sheet CD74ACT175 Quadruple D-type Flip-Flop with Clear datasheet (Rev. A) PDF | HTML 08 May 2024
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 15 Dec 2022
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 Apr 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
Not available on TI.com
Package Pins CAD symbols, footprints & 3D models
PDIP (N) 16 Ultra Librarian
SOIC (D) 16 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

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Information included:
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