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CDCE6214Q1TM

ACTIVE

Ultra-low power clock generator supporting PCIe® gen 1-5 with active low output enable

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Data sheet

CDCE6214Q1TM

ACTIVE
Data sheet Order now

Product details

Number of outputs 4 Output type HCSL, LVCMOS, LVDS Output frequency (max) (MHz) 328.125 Core supply voltage (V) 1.8, 2.5, 3.3 Output supply voltage (V) 1.8, 2.5, 3.3 Input type Differential, LVCMOS, XTAL Operating temperature range (°C) -40 to 105 TI functional safety category Functional Safety-Capable Features Integrated EEPROM, Pin programmable, Serial interface Rating Automotive
Number of outputs 4 Output type HCSL, LVCMOS, LVDS Output frequency (max) (MHz) 328.125 Core supply voltage (V) 1.8, 2.5, 3.3 Output supply voltage (V) 1.8, 2.5, 3.3 Input type Differential, LVCMOS, XTAL Operating temperature range (°C) -40 to 105 TI functional safety category Functional Safety-Capable Features Integrated EEPROM, Pin programmable, Serial interface Rating Automotive
VQFN (RGE) 24 16 mm² 4 x 4
  • AEC-Q100 qualified for automotive applications
    • Temperature grade 2: –40°C to +105°C
  • Functional Safety-Capable
  • Configurable high performance, low-power, frac-N PLL with RMS jitter with spurs (12 kHz – 20 MHz, F out > 100 MHz) as:
    • Integer mode:
      • Differential output: 350 fs typical, 600 fs maximum
      • LVCMOS output: 1.05 ps typical, 1.5 ps maximum
    • Fractional mode:
      • Differential output: 1.7 ps typical, 2.1 ps maximum
      • LVCMOS output: 2.0 ps typical, 4.0 ps maximum
  • Supports PCIe Gen1/2/3/4 with SSC and Gen 1/2/3/4/5 without SSC
  • Internal VCO: 2.335 GHz to 2.625 GHz
  • Typical power consumption: 65 mA for 4-output channel, 23 mA for 1-output channel.
  • Universal clock input, two reference inputs for redundancy
    • Differential AC-coupled or LVCMOS: 10 MHz to 200 MHz
    • Crystal: 10 MHz to 50 MHz
  • Flexible output clock distribution
    • Four channel dividers: Up to five unique output frequencies from 24 kHz to 328.125 MHz
    • Combination of LVDS-like, LP-HCSL or LVCMOS outputs on OUT0 – OUT4 pins
    • Glitchless output divider switching and output channel synchronization
    • Individual output enable through active-low GPIO and register
  • Frequency margining options
    • DCO mode: frequency increment/decrement with 10ppb or less step-size
  • Fully-integrated, configurable loop bandwidth: 100 kHz to 1.6 MHz
  • Single or mixed supply for level translation: 1.8 V, 2.5 V, 3.3 V
  • Configurable GPIOs and flexible configuration options
    • I 2C-compatible interface: up to 400 kHz
    • Integrated EEPROM with two pages and external select pin. In-situ programming allowed.
  • Supports 100-Ω systems
  • Low electromagnetic emissions
  • Small footprint: 24-pin VQFN (4 mm × 4 mm)
  • AEC-Q100 qualified for automotive applications
    • Temperature grade 2: –40°C to +105°C
  • Functional Safety-Capable
  • Configurable high performance, low-power, frac-N PLL with RMS jitter with spurs (12 kHz – 20 MHz, F out > 100 MHz) as:
    • Integer mode:
      • Differential output: 350 fs typical, 600 fs maximum
      • LVCMOS output: 1.05 ps typical, 1.5 ps maximum
    • Fractional mode:
      • Differential output: 1.7 ps typical, 2.1 ps maximum
      • LVCMOS output: 2.0 ps typical, 4.0 ps maximum
  • Supports PCIe Gen1/2/3/4 with SSC and Gen 1/2/3/4/5 without SSC
  • Internal VCO: 2.335 GHz to 2.625 GHz
  • Typical power consumption: 65 mA for 4-output channel, 23 mA for 1-output channel.
  • Universal clock input, two reference inputs for redundancy
    • Differential AC-coupled or LVCMOS: 10 MHz to 200 MHz
    • Crystal: 10 MHz to 50 MHz
  • Flexible output clock distribution
    • Four channel dividers: Up to five unique output frequencies from 24 kHz to 328.125 MHz
    • Combination of LVDS-like, LP-HCSL or LVCMOS outputs on OUT0 – OUT4 pins
    • Glitchless output divider switching and output channel synchronization
    • Individual output enable through active-low GPIO and register
  • Frequency margining options
    • DCO mode: frequency increment/decrement with 10ppb or less step-size
  • Fully-integrated, configurable loop bandwidth: 100 kHz to 1.6 MHz
  • Single or mixed supply for level translation: 1.8 V, 2.5 V, 3.3 V
  • Configurable GPIOs and flexible configuration options
    • I 2C-compatible interface: up to 400 kHz
    • Integrated EEPROM with two pages and external select pin. In-situ programming allowed.
  • Supports 100-Ω systems
  • Low electromagnetic emissions
  • Small footprint: 24-pin VQFN (4 mm × 4 mm)

The CDCE6214Q1TM is a 4-channel, ultra-low power, medium grade jitter, clock generator for automotive application that can generate five independent clock outputs selectable between various modes of drivers. The input source can be a single-ended or differential input clock source, or a crystal. The CDCE6214Q1TM features a frac-N PLL to synthesize unrelated base frequency from any input frequency.

The CDCE6214Q1TM is a 4-channel, ultra-low power, medium grade jitter, clock generator for automotive application that can generate five independent clock outputs selectable between various modes of drivers. The input source can be a single-ended or differential input clock source, or a crystal. The CDCE6214Q1TM features a frac-N PLL to synthesize unrelated base frequency from any input frequency.
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* Data sheet CDCE6214Q1TM Ultra-Low Power Clock Generator With One PLL, Four Differential Outputs, Two Inputs, and Internal EEPROM datasheet PDF | HTML 27 Jun 2023
Application note Clocking for PCIe Applications PDF | HTML 28 Nov 2023
Functional safety information CDCE6214-Q1 Functional Safety, FIT Rate, Failure Mode Distribution and Pin FMA PDF | HTML 15 Apr 2021

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Evaluation board

CDCE6214-Q1EVM — 4 differential and 1 LVCMOS outputs clock generator evaluation module

The CDCE6214-Q1 evalution module (EVM) is an evaluation platform for the CDCE6214-Q1 ultra-low power clock generator. This
evaluation module provides an USB-based interface to access the I2C bus to communicate with the CDCE6214-Q1. Pin control mode can set the device in a specific operation
User guide: PDF
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