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CDCLVD1204

ACTIVE

Low jitter, 2-input selectable 1:4 universal-to-LVDS buffer

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Data sheet

CDCLVD1204

ACTIVE
Data sheet Order now

Product details

Number of outputs 4 Additive RMS jitter (typ) (fs) 171 Core supply voltage (V) 2.5 Output supply voltage (V) 2.5 Output skew (ps) 20 Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVDS Input type LVCMOS, LVDS, LVPECL
Number of outputs 4 Additive RMS jitter (typ) (fs) 171 Core supply voltage (V) 2.5 Output supply voltage (V) 2.5 Output skew (ps) 20 Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVDS Input type LVCMOS, LVDS, LVPECL
VQFN (RGT) 16 9 mm² 3 x 3
  • 2:4 differential buffer
  • Low additive jitter: <300fs RMS in 10kHz to 20MHz
  • Low output skew of 20ps (maximum)
  • Universal inputs accept LVDS, LVPECL, and LVCMOS
  • Selectable clock inputs through control pin
  • 4 LVDS outputs, ANSI EIA/TIA-644A standard compatible
  • Clock frequency: up to 800MHz
  • Device power supply: 2.375V to 2.625V
  • LVDS reference voltage, VAC_REF, available for capacitive coupled inputs
  • Industrial temperature range: –40°C to 85°C
  • Packaged in 3mm × 3mm, 16-Pin VQFN (RGT)
  • ESD protection exceeds 3kV HBM, 1kV CDM
  • 2:4 differential buffer
  • Low additive jitter: <300fs RMS in 10kHz to 20MHz
  • Low output skew of 20ps (maximum)
  • Universal inputs accept LVDS, LVPECL, and LVCMOS
  • Selectable clock inputs through control pin
  • 4 LVDS outputs, ANSI EIA/TIA-644A standard compatible
  • Clock frequency: up to 800MHz
  • Device power supply: 2.375V to 2.625V
  • LVDS reference voltage, VAC_REF, available for capacitive coupled inputs
  • Industrial temperature range: –40°C to 85°C
  • Packaged in 3mm × 3mm, 16-Pin VQFN (RGT)
  • ESD protection exceeds 3kV HBM, 1kV CDM

The CDCLVD1204 clock buffer distributes one of two selectable clock inputs (IN0 and IN1) to 4 pairs of differential LVDS clock outputs (OUT0 through OUT3) with minimum skew for clock distribution. The CDCLVD1204 can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL, or LVCMOS.

The CDCLVD1204 is specifically designed for driving 50Ω transmission lines. In case of driving the inputs in single ended mode, the appropriate bias voltage, VAC_REF, must be applied to the unused negative input pin.

The IN_SEL pin selects the input which is routed to the outputs. If this pin is left open, it disables the outputs (static). The part supports a fail safe function. The device incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

The device operates in 2.5V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD1204 is packaged in small, 16-pin, 3mm × 3mm VQFN package.

The CDCLVD1204 clock buffer distributes one of two selectable clock inputs (IN0 and IN1) to 4 pairs of differential LVDS clock outputs (OUT0 through OUT3) with minimum skew for clock distribution. The CDCLVD1204 can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL, or LVCMOS.

The CDCLVD1204 is specifically designed for driving 50Ω transmission lines. In case of driving the inputs in single ended mode, the appropriate bias voltage, VAC_REF, must be applied to the unused negative input pin.

The IN_SEL pin selects the input which is routed to the outputs. If this pin is left open, it disables the outputs (static). The part supports a fail safe function. The device incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

The device operates in 2.5V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD1204 is packaged in small, 16-pin, 3mm × 3mm VQFN package.
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Technical documentation

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* Data sheet CDCLVD1204 2:4 Low Additive Jitter LVDS Buffer datasheet (Rev. C) PDF | HTML 14 May 2026
Application note Sine to Square Wave Conversion Using Clock Buffers PDF | HTML 03 Sep 2024
Application note Clocking Design Guidelines: Unused Pins 19 Nov 2015
User guide Low-Additive Jitter, Four LVDS Outputs Clock Buffer Evaluation Board 14 Jun 2010

Design & development

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Evaluation board

CDCLVD1204EVM — CDCLVD1204 Evaluation Module

The CDCLVD1204/CDCLVD2102 are high-performance, low-additive jitter clock buffers. They have twouniversal input buffers that support single-ended or differential clock inputs and are selectable through a control pin (for CDCLVD1204 only). The devices also feature on-chip bias generators that can (...)
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CDCLVD1204 IBIS Model (Rev. B)

SLLM089B.ZIP (14 KB) - IBIS Model
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PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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