Home Clocks & timing Clock buffers
Home
Clocks & timing
Clock buffers

CDCLVP110

ACTIVE

1:10 LVPECL/HSTL to LVPECL clock driver

Order now
Data sheet

CDCLVP110

ACTIVE
Data sheet Order now

Product details

Function Differential Additive RMS jitter (typ) (fs) 300 Output frequency (max) (MHz) 3500 Number of outputs 10 Output supply voltage (V) 2.5, 3.3 Core supply voltage (V) 2.5, 3.3 Output skew (ps) 30 Features 1:10 fanout Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVPECL Input type HSTL, LVPECL
Function Differential Additive RMS jitter (typ) (fs) 300 Output frequency (max) (MHz) 3500 Number of outputs 10 Output supply voltage (V) 2.5, 3.3 Core supply voltage (V) 2.5, 3.3 Output skew (ps) 30 Features 1:10 fanout Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVPECL Input type HSTL, LVPECL
LQFP (VF) 32 81 mm² 9 x 9
  • Distributes One Differential Clock Input Pair
    LVPECL/HSTL to 10 Differential LVPECL Clock Outputs
  • Fully Compatible With LVECL/LVPECL/HSTL
  • Single Supply Voltage Required, ±3.3-V or ±2.5-V Supply
  • Selectable Clock Input Through CLK_SEL
  • Low-Output Skew (Typ 15 ps) for Clock-Distribution Applications
  • VBB Reference Voltage Output for Single-Ended Clocking
  • Available in a 32-Pin LQFP Package
  • Frequency Range From DC to 3.5 GHz
  • Pin-to-Pin Compatible With MC100 Series EP111, ES6111, LVEP111, PTN1111
  • Distributes One Differential Clock Input Pair
    LVPECL/HSTL to 10 Differential LVPECL Clock Outputs
  • Fully Compatible With LVECL/LVPECL/HSTL
  • Single Supply Voltage Required, ±3.3-V or ±2.5-V Supply
  • Selectable Clock Input Through CLK_SEL
  • Low-Output Skew (Typ 15 ps) for Clock-Distribution Applications
  • VBB Reference Voltage Output for Single-Ended Clocking
  • Available in a 32-Pin LQFP Package
  • Frequency Range From DC to 3.5 GHz
  • Pin-to-Pin Compatible With MC100 Series EP111, ES6111, LVEP111, PTN1111

The CDCLVP110 clock driver distributes one differential clock pair of either LVPECL or HSTL (selectable) input, (CLK0, CLK1) to ten pairs of differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution. The CDCLVP110 can accept two clock sources into an input multiplexer. The CLK0 input accepts either LVECL/LVPECL input signals, while CLK1 accepts an HSTL input signal when operated under LVPECL conditions. The CDCLVP110 is specifically designed for driving 50-Ω transmission lines.

The VBB reference voltage output is used if single-ended input operation is required. In this case the VBB pin should be connected to CLK0 and bypassed to GND via a 10-nF capacitor.

However, for high-speed performance up to 3.5 GHz, the differential mode is strongly recommended.

The CDCLVP110 is characterized for operation from –40°C to 85°C.

The CDCLVP110 clock driver distributes one differential clock pair of either LVPECL or HSTL (selectable) input, (CLK0, CLK1) to ten pairs of differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution. The CDCLVP110 can accept two clock sources into an input multiplexer. The CLK0 input accepts either LVECL/LVPECL input signals, while CLK1 accepts an HSTL input signal when operated under LVPECL conditions. The CDCLVP110 is specifically designed for driving 50-Ω transmission lines.

The VBB reference voltage output is used if single-ended input operation is required. In this case the VBB pin should be connected to CLK0 and bypassed to GND via a 10-nF capacitor.

However, for high-speed performance up to 3.5 GHz, the differential mode is strongly recommended.

The CDCLVP110 is characterized for operation from –40°C to 85°C.
filter Find other Clock buffers
Download View video with transcript Video

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 6
Type Title Date
* Data sheet Low-Voltage 1:10 LVPECL/HSTL With Selectable Input Clock Driver datasheet (Rev. D) 11 Jan 2011
Application note Clocking Design Guidelines: Unused Pins 19 Nov 2015
Application note AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C) 17 Oct 2007
Application note Advantage of Using TI's Lowest Jitter Differential Clock Buffer 20 Aug 2003
Application note DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CML 19 Feb 2003
Application note PCB Layout Guidelines for CDCLVP110 12 Jun 2002

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Simulation model

CDCLVP110 IBIS Model (Rev. A)

SCAC032A.ZIP (32 KB) - IBIS Model
Download
Design tool

CLOCK-TREE-ARCHITECT — Clock tree architect programming software

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
Design now
Design tool

PLLATINUMSIM-SW — PLLatinum Sim Tool

PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.

Supported products & hardware

Supported products & hardware

Products
RF PLLs & synthesizers
LMX1204 — 12.8-GHz RF buffer, multiplier and divider with JESD204B/C SYSREF support and phase synchronization LMX1214 — 1:5 18GHz RF buffer and divider with auxiliary clock LMX1906-SP — Radiation-hardness-assured (RHA) 15GHz buffer, multiplier and divider with SYSREF and FPGA clock LMX2430 — 3.0-GHz/0.8-GHz PLLatinum dual high frequency synthesizer for RF personal communications LMX2433 — 3.6-GHz/1.7-GHz PLLatinum dual high frequency synthesizer for RF personal communications LMX2434 — 5.0-GHz/2.5-GHz PLLatinum low power dual frequency synthesizer for RF personal communications LMX2470 — 2.6-GHz delta-sigma fractional-N PLL with 800-MHz integer-N PLL LMX2485 — 500-MHz to 3-GHz delta-sigma low power dual PLL for RF personal communications LMX2485E — 50-MHz to 3-GHz delta-sigma low power dual PLL for RF personal communications LMX2485Q-Q1 — 500MHz to 3GHz automotive delta-sigma low power dual PLL LMX2486 — 1-GHz to 4.5-GHz delta-sigma low power dual PLL for RF personal communications LMX2487 — 1 to 6-GHz delta-sigma low power dual PLLatinum frequency synthesizer with 3.0-GHz integer PLL LMX2487E — 3-GHz to 7.5-GHz delta-sigma low power dual PLL for RF personal communications LMX2491 — 6.4-GHz low noise fractional-N PLL with ramp/chirp generation LMX2492 — 500MHz to 14GHz wideband, low noise fractional-N PLL with ramp/chirp generation LMX2492-Q1 — Automotive grade 500-MHz to 14-GHz wideband, low noise fractional-N PLL with ramp/chirp generation LMX2531 — High performance frequency synthesizer system with integrated VCO LMX2541 — Ultra-low noise PLLatinum frequency synthesizer with integrated VCO LMX2571 — 1.34-GHz, low-power, extreme-temperature RF synthesizer with frequency-shift keying (FSK) modulation LMX2571-EP — Enhanced-product, 1.34-GHz, low-power, extreme-temperature RF synthesizer with FSK modulation LMX2572 — 6.4-GHz low-power wideband RF synthesizer LMX2572LP — 2-GHz low power wideband RF synthesizer with FSK modulation LMX2581 — 3.76-GHz wideband frequency synthesizer with integrated VCO LMX2581E — 3.8-GHz wideband frequency synthesizer with integrated VCO LMX2582 — 5.5-GHz high performance, wideband PLLatinum RF synthesizer LMX2592 — 9.8-GHz wideband frequency synthesizer with integrated VCO LMX2594 — 15-GHz wideband PLLatinum™ RF synthesizer with phase synchronization and JESD204B support LMX2595 — 20-GHz wideband RF synthesizer with phase synchronization & JESD204B support LMX2615-SP — Space grade 40-MHz to 15-GHz wideband synthesizer with phase synchronization and JESD204B support LMX2694-EP — Enhanced product 15-GHz RF synthesizer with phase synchronization TRF3765 — 300M-4800MHz Low Noise Integer-N/Fractional-N PLL with Integrated VCO and up to 8 Outputs
Clock buffers
CDCDB2000 — DB2000QL compliant 20-output clock buffer for PCIe® Gen 1 to Gen 5 CDCDB400 — 4-output clock buffer for PCIe® Gen 1 to Gen 6 CDCDB800 — 8-output clock buffer for PCIe® Gen 1 to Gen 6 CDCDB803 — 8-output clock buffer for PCIe® Gen 1 to Gen 6 with selectable SMBus addresses CDCLVC1102 — Low jitter, 1:2 LVCMOS fan-out clock buffer CDCLVC1103 — Low jitter, 1:3 LVCMOS fan-out clock buffer CDCLVC1104 — Low jitter, 1:4 LVCMOS fan-out clock buffer CDCLVC1106 — Low jitter, 1:6 LVCMOS fan-out clock buffer CDCLVC1108 — Low jitter, 1:8 LVCMOS fan-out clock buffer CDCLVC1110 — Low jitter, 1:10 LVCMOS fan-out clock buffer CDCLVC1112 — Low jitter, 1:12 LVCMOS fan-out clock buffer CDCLVC1310 — Universal input, 10-output low impedance LVCMOS buffer CDCLVD110 — 1-to-10 LVDS clock buffer up to 900-MHz with minimum skew for clock distribution CDCLVD110A — 1-to-10 LVDS clock buffer up to 1100-MHz with minimum skew for clock distribution CDCLVD1204 — Low jitter, 2-input selectable 1:4 universal-to-LVDS buffer CDCLVD1208 — Low jitter, 2-input selectable 1:8 universal-to-LVDS buffer CDCLVD1212 — Low jitter, 2-input selectable 1:12 universal-to-LVDS buffer CDCLVD1213 — Low jitter, 1:4 universal-to-LVDS buffer with selectable output divider CDCLVD1216 — Low jitter, 2-input selectable 1:16 universal-to-LVDS buffer CDCLVD2102 — Low jitter, dual 1:2 universal-to-LVDS buffer CDCLVD2104 — Low jitter, dual 1:4 universal-to-LVDS buffer CDCLVD2106 — Low jitter, dual 1:6 universal-to-LVDS buffer CDCLVD2108 — Low jitter, dual 1:8 universal-to-LVDS buffer CDCLVP110 — 1:10 LVPECL/HSTL to LVPECL clock driver CDCLVP1102 — Low jitter 1:2 universal-to-LVPECL buffer CDCLVP111 — 1:10 LVPECL buffer with selectable input CDCLVP111-EP — HiRel, 1:10 LVPECL buffer with selectable input CDCLVP111-SP — 1:10 high speed clock buffer with selectable input clock driver CDCLVP1204 — Low-jitter, two-input, selectable 1:4 universal-to-LVPECL buffer CDCLVP1208 — Low jitter, 2-input selectable 1:8 universal-to-LVPECL buffer CDCLVP1212 — Low jitter, 2-input selectable 1:12 universal-to-LVPECL buffer CDCLVP1216 — Low jitter, 2-input selectable 1:16 universal-to-LVPECL buffer CDCLVP2102 — Low jitter, dual 1:2 universal-to-LVPECL buffer CDCLVP2104 — Low jitter, dual 1:4 universal-to-LVPECL buffer CDCLVP2106 — Low jitter, dual 1:6 universal-to-LVPECL buffer CDCLVP2108 — Low jitter, dual 1:8 universal-to-LVPECL buffer CDCLVP215 — Dual 1:5 high speed LVPECL fan out buffer LMK00301 — 3-GHz, 10-output differential fanout buffer / level translator LMK00304 — 3.1-GHz differential clock buffer/level translator with 4 configurable outputs LMK00306 — 3.1-GHz differential clock buffer/level translator with 6 configurable outputs LMK00308 — 3.1-GHz differential clock buffer/level translator with 8 configurable outputs LMK00334 — 4-output PCIe® Gen1/Gen2/Gen3/Gen4/Gen5 clock buffer and level translator LMK00334-Q1 — Automotive 4-output PCIe® Gen1/Gen2/Gen3/Gen4/Gen5 clock buffer and level translator LMK00338 — 8-output PCIe® Gen1/Gen2/Gen3/Gen4/Gen5 clock buffer and level translator LMK1C1102 — 2-channel output LVCMOS 1.8-V buffer LMK1C1103 — 3-channel output LVCMOS 1.8-V buffer LMK1C1104 — 4-channel output LVCMOS 1.8-V buffer LMK1C1106 — 6-channel output LVCMOS 1.8-V buffer LMK1C1108 — 8-channel output LVCMOS 1.8-V buffer LMK1D1204 — 4-channel output LVDS 1.8-V buffer LMK1D1204P — 4-channel output LVDS 1.8-V, 2.5-V, and 3.3-V buffer with pin control LMK1D1208 — 8-channel output LVDS 1.8-V, 2.5-V, and 3.3-V buffer LMK1D1208I — 8-channel output, 1.8-V, 2.5-V, and 3.3-V LVDS buffer with I²C LMK1D1208P — 8-channel output 1.8-V, 2.5-V, and 3.3-V LVDS buffer with pin control LMK1D1212 — 12-channel output 1.8-V, 2.5-V, and 3.3-V LVDS buffer LMK1D1216 — 16-channel output 1.8-V, 2.5-V, and 3.3-V LVDS buffer LMK1D2102 — Dual bank 2-channel output LVDS 1.8-V, 2.5-V, and 3.3-V buffer LMK1D2102L — Low additive jitter LVDS buffer LMK1D2104 — Dual bank 4-channel output 1.8V, 2.5V and 3.3V LVDS buffer LMK1D2106 — Dual bank 6-channel output 1.8-V, 2.5-V, and 3.3-V LVDS buffer LMK1D2108 — Dual bank 8-channel output 1.8-V, 2.5-V, and 3.3-V LVDS buffer
Clock generators
LMK03318 — Ultra-low jitter clock generator family with single PLL LMK03328 — Ultra-low jitter clock generator family with two independent PLLs LMK03806 — Ultra-low jitter clock generator with 14 outputs
IQ demodulators
LMX8410L — High-Performance Mixer With Integrated Synthesizer
Clock jitter cleaners
LMK04208 — Ultra low-noise clock jitter cleaner with 6 programmable outputs LMK04368-EP — Enhanced product ultra-low-noise 3.2-GHz JESD204C jitter cleaner LMK04714-Q1 — Automotive, ultra low-noise 3.2-GHz, JESD204B and JESD204C dual-loop clock jitter cleaner LMK04803 — Low-noise clock jitter cleaner with dual cascaded PLLs and integrated 1.9-GHz VCO LMK04805 — Low-noise clock jitter cleaner with dual cascaded PLLs and integrated 2.2-GHz VCO LMK04806 — Low-noise clock jitter cleaner with dual cascaded PLLs and integrated 2.5-GHz VCO LMK04808 — Low-noise clock jitter cleaner with dual loop PLLs and integrated 2.9-GHz VCO LMK04816 — Three input low-noise clock jitter cleaner with dual loop PLLs LMK04821 — Ultra low jitter synthesizer and jitter cleaner with JESD204B support LMK04826 — Ultra low-noise JESD204B compliant clock jitter cleaner with integrated 1840 to1970-MHz VCO0 LMK04828 — Ultra low-noise JESD204B compliant clock jitter cleaner with integrated 2370 to 2630-MHz VCO0. LMK04828-EP — Ultra low-noise JESD204B compliant clock jitter cleaner with temperature range -55 to 105c LMK04832 — Ultra-low-noise, 3.2-GHz, 15-output, JESD204B clock jitter cleaner with dual loop LMK04832-SEP — Radiation-tolerant, 30-krad, ultra-low-noise, 3.2-GHz 15-output JESD204C clock jitter cleaner LMK04832-SP — Radiation-hardened-assured (RHA), ultra-low-noise, 3.2-GHz, 15-output clock jitter cleaner LMK04906 — Ultra low noise clock jitter cleaner/multiplier with 6 programmable outputs
Clock network synchronizers
LMK05028 — Low-jitter dual-channel network synchronizer clock LMK05318 — Ultra-low jitter single channel network synchronizer clock with BAW LMK05318B — Ultra-low jitter single channel network synchronizer clock with BAW LMK05318B-Q1 — Automotive ultra-low jitter network synchronizer and clock generator LMK5B33216 — 16-output, three DPLL and APLL, network synchronizer with integrated 2.5-GHz bulk-acoustic-wave VCO LMK5B33414 — 14-output, three DPLL and APLL, network synchronizer with integrated 2.5-GHz bulk-acoustic-wave VCO LMK5C33216 — Ultra-low jitter clock synchronizer with JESD204B for wireless communications with BAW LMK5C33216A — Three DPLL, three APLL, two-input and 16-output network synchronizer with JESD204B/C and BAW VCO
Hardware development
Evaluation board
LMK04832EVM — LMK04832 JESD204B Clock Jitter Cleaner/Clock Generator/Distribution Evaluation Module LMX2571EPEVM — LMX2571-EP evaluation module for 1.34-GHz, low-power, extreme-temperature RF synthesizer LMX2594PSEVM — LMX2594 evaluation module for 15-GHz RF synthesizer with multiple-device phase synchronization XMICR-3P-LMX2492 — LMX2492 X-MWblock evaluation modules XMICR-3P-LMX2572 — LMX2572 X-MWblock evaluation modules XMICR-3P-LMX2592 — LMX2592 X-MWblock evaluation modules XMICR-3P-LMX2594 — LMX2594 X-MWblock evaluation modules XMICR-3P-LMX2595 — LMX2595 X-MWblock evaluation modules
Software
Application software & framework
TICSPRO-SW — Texas Instruments Clocks and Synthesizers (TICS) Pro Software
IDE, configuration, compiler or debugger
CODELOADER — CodeLoader Software for device register programming
Support software
LMX9830-SW — LMX9830 Application Notes, Software, and Tools LMX9838-SW — LMX9838 Application Notes, Software, and Tools
Download options
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Request
Package Pins CAD symbols, footprints & 3D models
LQFP (VF) 32 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

View all forum topics

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos