Product details

Function Clock generator Number of outputs 9 Output frequency (max) (MHz) 1296 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Input type LVCMOS, LVPECL Output type LVDS, LVPECL Operating temperature range (°C) -40 to 85 Features Integrated VCO, uWire Rating Catalog
Function Clock generator Number of outputs 9 Output frequency (max) (MHz) 1296 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Input type LVCMOS, LVPECL Output type LVDS, LVPECL Operating temperature range (°C) -40 to 85 Features Integrated VCO, uWire Rating Catalog
WQFN (RHS) 48 49 mm² 7 x 7
  • Integrated VCO with Very Low Phase Noise Floor
  • Integrated Integer-N PLL with Outstanding Normalized Phase Noise Contribution of -224 dBc/Hz
  • VCO Divider Values of 2 to 8 (All Divides)
    • Bypassable with VCO Mux When Not in 0-delay Mode
  • Channel Divider Values of 1, 2 to 510 (Even Divides)
  • LVDS and LVPECL Clock Outputs
  • Partially Integrated Loop Filter
  • Dedicated Divider and Delay Blocks on Each Clock Output
  • 0-delay Outputs
  • Internal or External Feedback of Output Clock
  • Delay Blocks on N and R Phase Detector Inputs for Lead/Lag Global Skew Adjust
  • Pin Compatible Family of Clocking Devices
  • 3.15 to 3.45 V Operation
  • Package: 48 Pin WQFN (7.0 x 7.0 x 0.8 mm)
  • 200 fs RMS Clock Generator Performance (10 Hz to 20 MHz) with a clean input clock

All trademarks are the property of their respective owners.

  • Integrated VCO with Very Low Phase Noise Floor
  • Integrated Integer-N PLL with Outstanding Normalized Phase Noise Contribution of -224 dBc/Hz
  • VCO Divider Values of 2 to 8 (All Divides)
    • Bypassable with VCO Mux When Not in 0-delay Mode
  • Channel Divider Values of 1, 2 to 510 (Even Divides)
  • LVDS and LVPECL Clock Outputs
  • Partially Integrated Loop Filter
  • Dedicated Divider and Delay Blocks on Each Clock Output
  • 0-delay Outputs
  • Internal or External Feedback of Output Clock
  • Delay Blocks on N and R Phase Detector Inputs for Lead/Lag Global Skew Adjust
  • Pin Compatible Family of Clocking Devices
  • 3.15 to 3.45 V Operation
  • Package: 48 Pin WQFN (7.0 x 7.0 x 0.8 mm)
  • 200 fs RMS Clock Generator Performance (10 Hz to 20 MHz) with a clean input clock

All trademarks are the property of their respective owners.

The LMK03200 family of precision clock conditioners combine the functions of jitter cleaning/reconditioning, multiplication, and 0-delay distribution of a reference clock. The devices integrate a Voltage Controlled Oscillator (VCO), a high performance Integer-N Phase Locked Loop (PLL), a partially integrated loop filter, and up to eight outputs in various LVDS and LVPECL combinations.

The VCO output is optionally accessible on the Fout port. Internally, the VCO output goes through a VCO divider to feed the various clock distribution blocks.

Each clock distribution block includes a programmable divider, a phase synchronization circuit, a programmable delay, a clock output mux, and an LVDS or LVPECL output buffer. The PLL also features delay blocks to permit global phase adjustment of clock output phase. This allows multiple integer-related and phase-adjusted copies of the reference to be distributed to eight system components.

The clock conditioners come in a 48-pin WQFN package and are footprint compatible with other clocking devices in the same family.


The LMK03200 family of precision clock conditioners combine the functions of jitter cleaning/reconditioning, multiplication, and 0-delay distribution of a reference clock. The devices integrate a Voltage Controlled Oscillator (VCO), a high performance Integer-N Phase Locked Loop (PLL), a partially integrated loop filter, and up to eight outputs in various LVDS and LVPECL combinations.

The VCO output is optionally accessible on the Fout port. Internally, the VCO output goes through a VCO divider to feed the various clock distribution blocks.

Each clock distribution block includes a programmable divider, a phase synchronization circuit, a programmable delay, a clock output mux, and an LVDS or LVPECL output buffer. The PLL also features delay blocks to permit global phase adjustment of clock output phase. This allows multiple integer-related and phase-adjusted copies of the reference to be distributed to eight system components.

The clock conditioners come in a 48-pin WQFN package and are footprint compatible with other clocking devices in the same family.


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Technical documentation

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Type Title Date
* Data sheet LMK03200 Family Precision 0-Delay Clock Conditioner with Integrated VCO datasheet (Rev. C) 19 Apr 2013
EVM User's guide LMK03200 Family Precision 0-Delay Clock Conditioner with Integrated VCO Eval 26 Jan 2012
Design guide Clock Conditioner Owner's Manual 10 Nov 2006

Design & development

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Software programming tool

CODELOADER CodeLoader Device Register Programming v4.19.0

The CodeLoader 4 software is used to program the LMX PLLs and LMK timing devices through either the USB or line print terminal (LPT) port of a computer. This software also provides information on how to program the device by showing the bits that are actually sent.

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Hardware development
Evaluation board
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Support software

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Support software

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Supported products & hardware

Supported products & hardware

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RF PLLs & synthesizers
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Clock buffers
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Oscillators
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Clock jitter cleaners
LMK04100 Precision clock conditioners clock jitter cleaner with cascaded PLLs LMK04101 Jitter cleaner with integrated 1430 to 1570-MHz VCO:3 outputs for 2VPEC/LVPEC+4 outputs for LVCOMS LMK04102 Jitter cleaner with integrated 1600 to 1750-MHz VCO:3 outputs for 2VPEC/LVPEC+4 outputs for LVCOMS LMK04110 Jitter cleaner with integrated 1185 to 1296-MHz VCO:5 outputs for 2VPEC/LVPEC LMK04111 Jitter cleaner with integrated 1430 to 1570-MHz VCO:5 outputs for 2VPEC/LVPEC LMK04131 Jitter cleaner with integrated 1430 to 1570-MHz VCO:2 outputs for 2VPEC/LVPEC+LVDS+LVCOMS LMK04133 Jitter cleaner with integrated 1840 to 2160-MHz VCO:2 outputs for 2VPEC/LVPEC+LVDS+LVCOMS LMK04208 Ultra low-noise clock jitter cleaner with 6 programmable outputs LMK04228 Ultra low-noise clock jitter cleaner with dual loop PLLs LMK04368-EP Enhanced product ultra-low-noise 3.2-GHz JESD204C jitter cleaner LMK04610 Ultra low-noise and low power JESD204B compliant clock jitter cleaner with dual PLLs LMK04616 Ultra low-noise and low power JESD204B compliant clock jitter cleaner LMK04714-Q1 Automotive, ultra low-noise 3.2-GHz, JESD204B and JESD204C dual-loop clock jitter cleaner LMK04803 Low-noise clock jitter cleaner with dual cascaded PLLs and integrated 1.9-GHz VCO LMK04816 Three input low-noise clock jitter cleaner with dual loop PLLs LMK04821 Ultra low jitter synthesizer and jitter cleaner with JESD204B support LMK04826 Ultra low-noise JESD204B compliant clock jitter cleaner with integrated 1840 to1970-MHz VCO0 LMK04828 Ultra low-noise JESD204B compliant clock jitter cleaner with integrated 2370 to 2630-MHz VCO0. LMK04828-EP Ultra low-noise JESD204B compliant clock jitter cleaner with temperature range -55 to 105c LMK04832 Ultra-low-noise, 3.2-GHz, 15-output, JESD204B clock jitter cleaner with dual loop LMK04832-SEP Radiation-tolerant, 30-krad, ultra-low-noise, 3.2-GHz 15-output JESD204C clock jitter cleaner LMK04832-SP Radiation-hardened-assured (RHA), ultra-low-noise, 3.2-GHz, 15-output clock jitter cleaner
Clock network synchronizers
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Hardware development
Evaluation board
LMK03806BEVAL LMK03806B Evaluation Board LMK04208EVM Two Input, 6+1 Output, Clock Jitter Cleaner With Dual Cascaded PLLs and Integrated 2.9 GHz VCO LMK04616EVM LMK04616 Evaluation Module LMK04805BEVAL Clock Jitter Cleaner With Dual Cascaded PLLs and Integrated 2.2 GHz VCO LMK04806BEVAL Clock Jitter Cleaner With Dual Cascaded PLLs and Integrated 2.5 GHz VCO LMK04816BEVAL Three Input, Thirteen Output, Clock Jitter Cleaner with Dual Cascaded PLLs and Integrated 2.5 GHz VC LMK04826BEVM LMK04826BEVM Evaluation Module LMK04828BEVM LMK04828 evaluation module LMK04832EVM LMK04832 JESD204B Clock Jitter Cleaner/Clock Generator/Distribution Evaluation Module LMK04832SEPEVM LMK04832-SEP evaluation module for ultra-low-noise, 3.2-GHz 15-output clock jitter clea LMK04906BEVAL Three Input, Seven Output, Clock Jitter Cleaner with Dual Cascaded PLLs and Integrated 2.5 GHz VCO LMK5B33216EVM LMK5B33216 evaluation module for 16-output, three DPLL and APLL, network synchronizer with BAW VCO LMX2571EPEVM LMX2571-EP evaluation module for 1.34-GHz, low-power, extreme-temperature RF synthesizer LMX2582EVM LMX2582EVM High Performance, Wideband Frequency PLLatinum RF Synthesizer With Integrated VCO LMX2592EVM LMX2592EVM high-performance, wideband frequency RF synthesizer PLLATINUM™ integrated circuit LMX2594PSEVM LMX2594 evaluation module for 15-GHz RF synthesizer with multiple-device phase synchronization XMICR-3P-LMX2492 LMX2492 X-MWblock evaluation modules XMICR-3P-LMX2572 LMX2572 X-MWblock evaluation modules XMICR-3P-LMX2592 LMX2592 X-MWblock evaluation modules XMICR-3P-LMX2594 LMX2594 X-MWblock evaluation modules XMICR-3P-LMX2595 LMX2595 X-MWblock evaluation modules LMK04832EVM-CVAL LMK04832-SP evaluation module for ultra-low-noise, dual-loop, JESD204B clock jitter cleaner LMK04368EPEVM LMK04368-EP evaluation module for JESD204B/C dual-loop clock jitter cleaner LMK61E0MEVM LMK61E0M Ultra-Low-Jitter Programmabler Oscillator Evaluation Module LMK61E2EVM LMK61E2EVM Ultra-Low-Jitter Programmable Oscillator Evaluation Module LMX1204EVM LMX1204 evaluation module for RF buffer, multiplier and divider with JESD204B/C SYSREF support LMX2594EVM LMX2594EVM 15-GHz wideband RF synthesizer with phase synchronization & JESD204B evaluation module LMX2595EVM 20-GHz Wideband RF Synthesizer With Phase Synchronization and JESD204B Evaluation Module LMX2615EVM-CVAL Space grade synthesizer evaluation module LMX2694EPEVM 15-GHz wideband RF synthesizer evaluation module LMX2572EVM 6.4-GHz Low Power Wideband RF Synthesizer with Phase Synchronization and JESD204B Support LMX2572LPEVM 2-GHz Low Power Wideband RF Synthesizer with FSK Modulation Evaluation Module LMX2581EVM LMX2581 evaluation module LMX2820EVM LMX2820 22.6-GHz wideband RF synthesizer evaluation module LMX8410LEVM I/Q demodulator evaluation module LMK5B12212EVM LMK5B12212 evaluation module LMK5B33414EVM LMK5B33414 evaluation module for 14-output, three DPLL and APLL, network synchronizer with BAW VCO LMK5C33216AEVM LMK5C33216A evaluation module LMK5C33216EVM LMK5C33216 clock synchronizer DPLL 2 input 16 outputs evaluation module LMK5C33414AEVM LMK5C33414A evaluation module LMK05028EVM LMK05028 Network Clock Generator and Synchronizer Evaluation Module LMK05318BEVM Network synchronizer clock evaluation module CDCI6214EVM CDCI6214 Ultra-Low Power Clock Generator Evaluation Module CDCE6214-Q1EVM 4 differential and 1 LVCMOS outputs clock generator evaluation module LMK3H0102EVM LMK3H0102 evaluation module
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Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
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WQFN (RHS) 48 Ultra Librarian

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