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LMK1D1208I

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8-channel output, 1.8-V, 2.5-V, and 3.3-V LVDS buffer with I²C

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Data sheet

LMK1D1208I

ACTIVE
Data sheet Order now

Product details

Number of outputs 8 Additive RMS jitter (typ) (fs) 50 Core supply voltage (V) 1.8, 2.5, 3.3 Output supply voltage (V) 1.8, 2.5, 3.3 Output skew (ps) 20 Operating temperature range (°C) -40 to 105 Rating Catalog Output type LVDS Input type HCSL, LP-HCSL, LVCMOS, LVDS, LVPECL
Number of outputs 8 Additive RMS jitter (typ) (fs) 50 Core supply voltage (V) 1.8, 2.5, 3.3 Output supply voltage (V) 1.8, 2.5, 3.3 Output skew (ps) 20 Operating temperature range (°C) -40 to 105 Rating Catalog Output type LVDS Input type HCSL, LP-HCSL, LVCMOS, LVDS, LVPECL
VQFN (RHA) 40 36 mm² 6 x 6
  • High-performance LVDS clock buffer family with 2 inputs and 8 outputs
  • Output frequency up to 2 GHz
  • Supply voltage: 1.8 V / 2.5 V / 3.3 V ± 5%
  • Device configurability through I 2C programming

    • Individual input and output enable/disable

    • Individual output amplitude select (standard or boosted)

    • Bank input multiplexer

  • Four programmable I 2C addresses through IDX pins
  • Low additive jitter: < 60 fs RMS maximum in 12-kHz to 20-MHz at 156.25 MHz

    • Very low phase noise floor: -164 dBc/Hz (typical)

  • Very low propagation delay: < 575 ps maximum
  • Output skew: 20 ps maximum
  • Universal inputs accept LVDS, LVPECL, LVCMOS, HCSL and CML
  • Fail-safe inputs
  • LVDS reference voltage, V AC_REF, available for capacitive coupled inputs
  • Industrial temperature range: –40°C to 105°C
  • Packages available
    • 6-mm × 6-mm, 40-Pin VQFN (RHA)
  • High-performance LVDS clock buffer family with 2 inputs and 8 outputs
  • Output frequency up to 2 GHz
  • Supply voltage: 1.8 V / 2.5 V / 3.3 V ± 5%
  • Device configurability through I 2C programming

    • Individual input and output enable/disable

    • Individual output amplitude select (standard or boosted)

    • Bank input multiplexer

  • Four programmable I 2C addresses through IDX pins
  • Low additive jitter: < 60 fs RMS maximum in 12-kHz to 20-MHz at 156.25 MHz

    • Very low phase noise floor: -164 dBc/Hz (typical)

  • Very low propagation delay: < 575 ps maximum
  • Output skew: 20 ps maximum
  • Universal inputs accept LVDS, LVPECL, LVCMOS, HCSL and CML
  • Fail-safe inputs
  • LVDS reference voltage, V AC_REF, available for capacitive coupled inputs
  • Industrial temperature range: –40°C to 105°C
  • Packages available
    • 6-mm × 6-mm, 40-Pin VQFN (RHA)

The LMK1D1208I is an I 2C-programmable LVDS clock buffer. The device has two inputs and eight pairs of differential LVDS clock outputs (OUT0 through OUT7) with minimum skew for clock distribution. The inputs can either be LVDS, LVPECL, LVCMOS, HCSL, or CML.

The LMK1D1208I is specifically designed for driving 50-Ω transmission lines. When driving inputs in single-ended mode, apply the appropriate bias voltage to the unused negative input pin.

I 2C programming enables this device to be configured as a single bank buffer (one of the two inputs is distributed to eight output pairs) or as a dual bank buffer (each input is distributed to four outputs pairs). Each output can be configured to have either a standard (350 mV) or boosted (500 mV) swing. This device also incorporates individual output channel enable or disable through I 2C programming. The LMK1D1208I has fail-safe inputs that prevent oscillation at the outputs in the absence of an input signal and allows for input signals before VDD is supplied.

The device operates in a 1.8-V, 2.5-V, or 3.3-V supply environment and is characterized from –40°C to 105°C (ambient temperature).

The LMK1D1208I is an I 2C-programmable LVDS clock buffer. The device has two inputs and eight pairs of differential LVDS clock outputs (OUT0 through OUT7) with minimum skew for clock distribution. The inputs can either be LVDS, LVPECL, LVCMOS, HCSL, or CML.

The LMK1D1208I is specifically designed for driving 50-Ω transmission lines. When driving inputs in single-ended mode, apply the appropriate bias voltage to the unused negative input pin.

I 2C programming enables this device to be configured as a single bank buffer (one of the two inputs is distributed to eight output pairs) or as a dual bank buffer (each input is distributed to four outputs pairs). Each output can be configured to have either a standard (350 mV) or boosted (500 mV) swing. This device also incorporates individual output channel enable or disable through I 2C programming. The LMK1D1208I has fail-safe inputs that prevent oscillation at the outputs in the absence of an input signal and allows for input signals before VDD is supplied.

The device operates in a 1.8-V, 2.5-V, or 3.3-V supply environment and is characterized from –40°C to 105°C (ambient temperature).
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* Data sheet LMK1D1208I I2C-Configurable, Low-Additive Jitter LVDS Buffer datasheet (Rev. A) PDF | HTML 14 Jun 2023

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Evaluation board

LMK1D1208IEVM — LMK1D1208I evaluation module for 8-channel output, 1.8-V, 2.5-V, and 3.3-V LVDS buffer with I²C

The LMK1D1208I evaluation module (EVM) is designed to demonstrate the electrical performance of the LMK1D1208I. LMK1D1208I is an I2C-configurable high-performance, low-additive jitter LVDS clock buffer with two differential inputs and eight LVDS outputs. LMK1D1208IEVM is equipped with 50-Ω SMA (...)
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Texas Instruments clocks and synthesizers (TICS) pro software is used to program the evaluation modules (EVMs) for product numbers with these prefixes: CDC, LMK and LMX. These products include phase-locked loops and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.

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PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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