SN54ACT11

ACTIVE

Military, 3-ch, 3-input 4.5-V to 5.5-V 24-mA drive strength AND gate with TTL-compatible inputs

Product details

Technology family ACT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 3 Inputs per channel 3 IOL (max) (mA) 24 IOH (max) (mA) -24 Input type TTL-Compatible CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 90 Rating Military Operating temperature range (°C) -55 to 125
Technology family ACT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 3 Inputs per channel 3 IOL (max) (mA) 24 IOH (max) (mA) -24 Input type TTL-Compatible CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 90 Rating Military Operating temperature range (°C) -55 to 125
CFP (W) 14 58.023 mm² 9.21 x 6.3 LCCC (FK) 20 79.0321 mm² 8.89 x 8.89
  • 4.5V to 5.5V VCC operation
  • Inputs accept voltages to 5.5V
  • Max tpd of 10.5ns at 5V
  • Inputs are TTL-voltage compatible
  • 4.5V to 5.5V VCC operation
  • Inputs accept voltages to 5.5V
  • Max tpd of 10.5ns at 5V
  • Inputs are TTL-voltage compatible

The ’ACT11 devices contain three independent 3-input AND gates. These devices perform the Boolean function Y = A • B • C or Y = A + B + C in positive logic.

The ’ACT11 devices contain three independent 3-input AND gates. These devices perform the Boolean function Y = A • B • C or Y = A + B + C in positive logic.

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Technical documentation

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Type Title Date
* Data sheet SNx4ACT11 Triple 3-Input Positive-and Gates datasheet (Rev. D) PDF | HTML 26 Jul 2024
* SMD SN54ACT11 SMD 5962-90772 21 Jun 2016
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 Apr 1996

Design & development

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Package Pins CAD symbols, footprints & 3D models
CFP (W) 14 Ultra Librarian
LCCC (FK) 20 Ultra Librarian

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