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SN74AHC132

ACTIVE

4-ch 4-input 2-V to 5.5-V NAND gates with Schmitt-Trigger inputs

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Data sheet

SN74AHC132

ACTIVE
Data sheet Order now

Product details

Technology family AHC Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Number of channels 4 Inputs per channel 4 IOL (max) (mA) 8 IOH (max) (mA) -8 Input type Schmitt-Trigger Output type Push-Pull Features High speed (tpd 10- 50ns), Over-voltage tolerant inputs Data rate (max) (Mbps) 110 Rating Catalog Operating temperature range (°C) -40 to 125
Technology family AHC Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Number of channels 4 Inputs per channel 4 IOL (max) (mA) 8 IOH (max) (mA) -8 Input type Schmitt-Trigger Output type Push-Pull Features High speed (tpd 10- 50ns), Over-voltage tolerant inputs Data rate (max) (Mbps) 110 Rating Catalog Operating temperature range (°C) -40 to 125
PDIP (N) 14 181.42 mm² 19.3 x 9.4 SOIC (D) 14 51.9 mm² 8.65 x 6 SOP (NS) 14 79.56 mm² 10.2 x 7.8 SSOP (DB) 14 48.36 mm² 6.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4 TVSOP (DGV) 14 23.04 mm² 3.6 x 6.4 VQFN (RGY) 14 12.25 mm² 3.5 x 3.5 WQFN (BQA) 14 7.5 mm² 3 x 2.5
  • Operating range 2V to 5.5V VCC
  • Operation from very slow input transitions
  • Temperature-compensated threshold levels
  • High noise immunity
  • Same pinouts as SNx4AHC00
  • Latch-up performance exceeds 250mAper JESD 17
  • ESD protection exceeds JESD 22
    • 2000V human-body model
    • 1000V charged-device model
  • Operating range 2V to 5.5V VCC
  • Operation from very slow input transitions
  • Temperature-compensated threshold levels
  • High noise immunity
  • Same pinouts as SNx4AHC00
  • Latch-up performance exceeds 250mAper JESD 17
  • ESD protection exceeds JESD 22
    • 2000V human-body model
    • 1000V charged-device model

The SN7AHC132 device is a quadruple positive-NAND gate designed for 2V to 5.5V VCC operation. This device performs the Boolean functionY = A × B or Y = A + B in positive logic.

Schmitt-trigger inputs provide added noise immunity and support for slow input signal transitions.

The SN7AHC132 device is a quadruple positive-NAND gate designed for 2V to 5.5V VCC operation. This device performs the Boolean functionY = A × B or Y = A + B in positive logic.

Schmitt-trigger inputs provide added noise immunity and support for slow input signal transitions.
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Technical documentation

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Type Title Date
* Data sheet SN74AHC132 Quadruple Positive-NAND Gates with Schmitt-Trigger Inputs datasheet (Rev. K) PDF | HTML 27 Feb 2024
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Little Logic Guide 2018 (Rev. G) 06 Jul 2018
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note How to Select Little Logic (Rev. A) 26 Jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
Analog Design Journal Discrete design of a low-cost isolated 3.3- to 5-V DC/DC converter 06 May 2010
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Product overview Design Summary for WCSP Little Logic (Rev. B) 04 Nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
Application note Advanced High-Speed CMOS (AHC) Logic Family (Rev. C) 02 Dec 2002
Application note Texas Instruments Little Logic Application Report 01 Nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Design guide AHC/AHCT Designer's Guide February 2000 (Rev. D) 24 Feb 2000
Application note Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A) 08 Sep 1999
Product overview Military Advanced High-Speed CMOS Logic (AHC/AHCT) (Rev. C) 01 Apr 1998
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 Dec 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Live Insertion 01 Oct 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
Not available on TI.com
Evaluation board

14-24-NL-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin non-leaded packages

14-24-NL-LOGIC-EVM is a flexible evaluation module (EVM) designed to support any logic or translation device that has a 14-pin to 24-pin BQA, BQB, RGY, RSV, RJW or RHL package.

User guide: PDF | HTML
Not available on TI.com
Simulation model

SN74AHC132 Behavioral SPICE Model

SCLM280.ZIP (7 KB) - PSpice Model
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Package Pins CAD symbols, footprints & 3D models
PDIP (N) 14 Ultra Librarian
SOIC (D) 14 Ultra Librarian
SOP (NS) 14 Ultra Librarian
SSOP (DB) 14 Ultra Librarian
TSSOP (PW) 14 Ultra Librarian
TVSOP (DGV) 14 Ultra Librarian
VQFN (RGY) 14 Ultra Librarian
WQFN (BQA) 14 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

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