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SN74AUP1G00

ACTIVE

Single 1-input, 0.8-V to 3.6-V low power NAND gate

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Data sheet

SN74AUP1G00

ACTIVE
Data sheet Order now

Product details

Technology family AUP Number of channels 1 Inputs per channel 2 IOL (max) (mA) 4 IOH (max) (mA) -4 Input type Standard CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 100 Rating Catalog Operating temperature range (°C) -40 to 85
Technology family AUP Number of channels 1 Inputs per channel 2 IOL (max) (mA) 4 IOH (max) (mA) -4 Input type Standard CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 100 Rating Catalog Operating temperature range (°C) -40 to 85
SOT-5X3 (DRL) 5 2.56 mm² (1.6 mm × 1.6 mm) USON (DRY) 6 1.45 mm² (1.45 mm × 1 mm) X2SON (DSF) 6 1 mm² (1 mm × 1 mm) DSBGA (YFP) 6 1.4000000000000001 mm² (— mm × — mm) SOT-SC70 (DCK) 5 4.2 mm² (2 mm × 2.1 mm) X2SON (DPW) 5 0.64 mm² (0.8 mm × 0.8 mm) SOT-23 (DBV) 5 8.12 mm² (2.9 mm × 2.8 mm)
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Available in the Ultra Small 0.64 mm2 Package (DPW) with 0.5-mm Pitch
  • Low Static-Power Consumption (ICC = 0.9 µA Max)
  • Low Dynamic-Power Consumption (Cpd = 4 pF Typical at 3.3 V)
  • Low Input Capacitance (Ci = 1.5 pF Typical)
  • Low Noise Overshoot and Undershoot <10% of VCC
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
  • Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at Input (Vhys = 250 mV Typical at 3.3 V)
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • Optimized for 3.3-V Operation
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • tpd = 4.8 ns Maximum at 3.3 V
  • Suitable for Point-to-Point Applications
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Available in the Ultra Small 0.64 mm2 Package (DPW) with 0.5-mm Pitch
  • Low Static-Power Consumption (ICC = 0.9 µA Max)
  • Low Dynamic-Power Consumption (Cpd = 4 pF Typical at 3.3 V)
  • Low Input Capacitance (Ci = 1.5 pF Typical)
  • Low Noise Overshoot and Undershoot <10% of VCC
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
  • Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at Input (Vhys = 250 mV Typical at 3.3 V)
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • Optimized for 3.3-V Operation
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • tpd = 4.8 ns Maximum at 3.3 V
  • Suitable for Point-to-Point Applications
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

This single 2-input positive-NAND gate performs the Boolean function Y = A × B or Y = A + B in positive logic.

This single 2-input positive-NAND gate performs the Boolean function Y = A × B or Y = A + B in positive logic.
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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet SN74AUP1G00 Low-Power Single 2-Input Positive-NAND Gate datasheet (Rev. J) PDF | HTML Dec 7, 2016
Application brief Understanding Schmitt Triggers (Rev. B) PDF | HTML Apr 17, 2025
Application note Designing and Manufacturing with TI's X2SON Packages Aug 23, 2017

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Simulation model

SN74AUP1G00 Behavioral SPICE Model

SCEM695.ZIP (7 KB) - PSpice model
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Simulation model

SN74AUP1G00 IBIS Model (Rev. A)

SCEM461 (356 KB) - IBIS model
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Supported products & hardware
Package Pins CAD symbols, footprints & 3D models
SOT-5X3 (DRL) 5 Ultra Librarian
USON (DRY) 6 Ultra Librarian
X2SON (DSF) 6 Ultra Librarian
DSBGA (YFP) 6 Ultra Librarian
SOT-SC70 (DCK) 5 Ultra Librarian
X2SON (DPW) 5 Ultra Librarian
SOT-23 (DBV) 5 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

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