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Voltage translating gates

SN74AUP1T86

ACTIVE

Low Power, 1.8/2.5/3.3-V Input, 3.3-V CMOS Output, 2-Input Exclusive-OR Gate

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Data sheet

SN74AUP1T86

ACTIVE
Data sheet Order now

Product details

Technology family AUP1T Number of channels 1 Vout (min) (V) 2.3 Vout (max) (V) 3.6 Data rate (max) (Mbps) 200 IOH (max) (mA) -4 IOL (max) (mA) 4 Supply current (max) (µA) 0.9 Features Over-voltage tolerant inputs, Partial power down (Ioff), Single supply, Voltage translation Input type Schmitt-Trigger Output type Balanced CMOS, Push-Pull Operating temperature range (°C) -40 to 85
Technology family AUP1T Number of channels 1 Vout (min) (V) 2.3 Vout (max) (V) 3.6 Data rate (max) (Mbps) 200 IOH (max) (mA) -4 IOL (max) (mA) 4 Supply current (max) (µA) 0.9 Features Over-voltage tolerant inputs, Partial power down (Ioff), Single supply, Voltage translation Input type Schmitt-Trigger Output type Balanced CMOS, Push-Pull Operating temperature range (°C) -40 to 85
SOT-SC70 (DCK) 5 4.2 mm² 2 x 2.1
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Technical documentation

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Type Title Date
* Data sheet Low Power, 1.8/2.5/3.3-V Input, 3.3-V CMOS Output, 2-Input Exclusive-OR Gate datasheet (Rev. A) 09 Mar 2018
Selection guide Voltage Translation Buying Guide (Rev. A) 15 Apr 2021
Application brief Understanding Schmitt Triggers (Rev. A) PDF | HTML 22 May 2019

Design & development

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Evaluation board

5-8-LOGIC-EVM — Generic logic evaluation module for 5-pin to 8-pin DCK, DCT, DCU, DRL and DBV packages

Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
User guide: PDF
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Package Pins CAD symbols, footprints & 3D models
SOT-SC70 (DCK) 5 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

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