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Noninverting buffers & drivers

SN74AUP2G07

ACTIVE

2-ch, 0.8-V to 3.6-V low power buffers with open-drain outputs

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Data sheet

SN74AUP2G07

ACTIVE
Data sheet Order now

Product details

Technology family AUP Number of channels 2 IOL (max) (mA) 4 Supply current (max) (µA) 0.9 IOH (max) (mA) 0 Input type Standard CMOS Output type Open-drain Features Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 85
Technology family AUP Number of channels 2 IOL (max) (mA) 4 Supply current (max) (µA) 0.9 IOH (max) (mA) 0 Input type Standard CMOS Output type Open-drain Features Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 85
X2SON (DSF) 6 1 mm² (1 mm × 1 mm) SOT-SC70 (DCK) 6 4.2 mm² (2 mm × 2.1 mm) DSBGA (YFP) 6 1.4000000000000001 mm² (— mm × — mm) USON (DRY) 6 1.45 mm² (1.45 mm × 1 mm)
  • Low static-power consumption (ICC = 0.9 µA maximum)
  • Low dynamic-power consumption (Cpd = 1 pF typical at 3.3 V)
  • Low input capacitance (Ci = 1.5 pF typical)
  • Low noise – overshoot and undershoot <10% of VCC
  • Ioff supports live insertion, partial-power-down mode, and back-drive protection
  • Input hysteresis allows slow input transition and better switching noise immunity at the input (Vhys = 250 mV typical at 3.3 V)
  • Wide operating VCC range of 0.8 V to 3.6 V
  • Optimized for 3.3 V operation
  • 3.6-V I/O tolerant to support mixed-mode signal operation
  • tpd = 3.3 ns maximum at 3.3 V
  • Suitable for point-to-point applications
  • Latch-up performance exceeds 100 mA per JESD 78, Class II
  • ESD performance tested per JESD 22
    • 4500-V human-body model
    • 1500-V charged-device model
  • Low static-power consumption (ICC = 0.9 µA maximum)
  • Low dynamic-power consumption (Cpd = 1 pF typical at 3.3 V)
  • Low input capacitance (Ci = 1.5 pF typical)
  • Low noise – overshoot and undershoot <10% of VCC
  • Ioff supports live insertion, partial-power-down mode, and back-drive protection
  • Input hysteresis allows slow input transition and better switching noise immunity at the input (Vhys = 250 mV typical at 3.3 V)
  • Wide operating VCC range of 0.8 V to 3.6 V
  • Optimized for 3.3 V operation
  • 3.6-V I/O tolerant to support mixed-mode signal operation
  • tpd = 3.3 ns maximum at 3.3 V
  • Suitable for point-to-point applications
  • Latch-up performance exceeds 100 mA per JESD 78, Class II
  • ESD performance tested per JESD 22
    • 4500-V human-body model
    • 1500-V charged-device model

The SN74AUP2G07 device is a dual buffer gate with open drain output that operates from 0.8 V to 3.6 V.

The SN74AUP2G07 device is a dual buffer gate with open drain output that operates from 0.8 V to 3.6 V.
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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet SN74AUP2G07 Low-Power Dual Buffer/Driver With Open-Drain Outputs datasheet (Rev. E) PDF | HTML Oct 4, 2021
Application brief Understanding Schmitt Triggers (Rev. B) PDF | HTML Apr 17, 2025

Design & development

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Evaluation board

5-8-LOGIC-EVM — Generic logic evaluation module for 5-pin to 8-pin DCK, DCT, DCU, DRL and DBV packages

Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
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Evaluation board

5-8-NL-LOGIC-EVM — Generic logic and translation EVM supporting 5 to 8 pin DPW, DQE, DRY, DSF, DTM, DTQ and DTT pkgs

Generic EVM designed to support any logic or translation device that has a DTT, DRY, DPW, DTM, DQE, DQM, DSF, or DTQ package. Board design allows for flexible evaluation.

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Simulation model

SN74AUP2G07 Behavioral SPICE Model

SCEM677.ZIP (7 KB) - PSpice model
Supported products & hardware
Simulation model

SN74AUP2G07 PSpice Model

SCEM577.ZIP (50 KB) - PSpice model
Supported products & hardware
Package Pins CAD symbols, footprints & 3D models
X2SON (DSF) 6 Ultra Librarian
SOT-SC70 (DCK) 6 Ultra Librarian
DSBGA (YFP) 6 Ultra Librarian
USON (DRY) 6 Ultra Librarian
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