SN74HC590A

Name: SN74HC590A
Brand: TI
SKU: SN74HC590A
Price: 0.182 USD

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8-Bit Binary Counters With 3-State Output Registers

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Data sheet

document-pdfAcrobat SN54HC590A, SN74HC590A datasheet (Rev. F)

SN74HC590A

ACTIVE

Data sheet

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Product details

Function

Counter

Bits (#)

8

Technology family

HC

Supply voltage (min) (V)

2

Supply voltage (max) (V)

6

Input type

LVTTL/CMOS

Output type

CMOS

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Function

Counter

Bits (#)

8

Technology family

HC

Supply voltage (min) (V)

2

Supply voltage (max) (V)

6

Input type

LVTTL/CMOS

Output type

CMOS

Operating temperature range (°C)

-40 to 85

Rating

Catalog

PDIP (N)

16

181.42 mm² 19.3 x 9.4

SOIC (D)

16

59.4 mm² 9.9 x 6

SOIC (DW)

16

106.09 mm² 10.3 x 10.3

2-V to 6-V V_CC Operation
High-Current 3-State Parallel Register Outputs Can Drive Up to 15 LSTTL Loads
Low Power Consumption, 80-µA Max I_CC
Typical t_pd = 14 ns
±6-mA Output Drive at 5 V
Low Input Current of 1 µA Max
8-Bit Counter With Register
Counter Has Direct Clear

2-V to 6-V V_CC Operation
High-Current 3-State Parallel Register Outputs Can Drive Up to 15 LSTTL Loads
Low Power Consumption, 80-µA Max I_CC
Typical t_pd = 14 ns
±6-mA Output Drive at 5 V
Low Input Current of 1 µA Max
8-Bit Counter With Register
Counter Has Direct Clear

The 'HC590A devices contain an 8-bit binary counter that feeds an 8-bit storage register. The storage register has parallel outputs. Separate clocks are provided for both the binary counter and storage register. The binary counter features direct clear (CCLR)\ and count-enable (CCKEN)\ inputs. A ripple-carry output (RCO)\ is provided for cascading. Expansion is accomplished easily for two stages by connecting RCO\ of the first stage to CCKEN\ of the second stage. Cascading for larger count chains can be accomplished by connecting RCO\ of each stage to the counter clock (CCLK) input of the following stage.

CCLK and the register clock (RCLK) inputs are positive-edge triggered. If both clocks are connected together, the counter state always is one count ahead of the register. Internal circuitry prevents clocking from the clock enable.

The 'HC590A devices contain an 8-bit binary counter that feeds an 8-bit storage register. The storage register has parallel outputs. Separate clocks are provided for both the binary counter and storage register. The binary counter features direct clear (CCLR)\ and count-enable (CCKEN)\ inputs. A ripple-carry output (RCO)\ is provided for cascading. Expansion is accomplished easily for two stages by connecting RCO\ of the first stage to CCKEN\ of the second stage. Cascading for larger count chains can be accomplished by connecting RCO\ of each stage to the counter clock (CCLK) input of the following stage.

CCLK and the register clock (RCLK) inputs are positive-edge triggered. If both clocks are connected together, the counter state always is one count ahead of the register. Internal circuitry prevents clocking from the clock enable.

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