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SN74HCS174

ACTIVE

Logic hex D-type flip-flops with reset

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Data sheet

SN74HCS174

ACTIVE
Data sheet Order now

Product details

Number of channels 6 Technology family HCS Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Input type Schmitt-Trigger Output type Push-Pull Clock frequency (max) (MHz) 130 IOL (max) (mA) 7.8 IOH (max) (mA) -7.8 Supply current (max) (µA) 2 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -40 to 125 Rating Catalog
Number of channels 6 Technology family HCS Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Input type Schmitt-Trigger Output type Push-Pull Clock frequency (max) (MHz) 130 IOL (max) (mA) 7.8 IOH (max) (mA) -7.8 Supply current (max) (µA) 2 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -40 to 125 Rating Catalog
SOIC (D) 16 59.4 mm² 9.9 x 6 TSSOP (PW) 16 32 mm² 5 x 6.4
  • Wide operating voltage range: 2 V to 6 V
  • Schmitt-trigger inputs allow for slow or noisy input signals
  • Low power consumption
    • Typical ICC of 100 nA
    • Typical input leakage current of ±100 nA
  • ±7.8-mA output drive at 6 V
  • Extended ambient temperature range: –40°C to +125°C, TA
  • Wide operating voltage range: 2 V to 6 V
  • Schmitt-trigger inputs allow for slow or noisy input signals
  • Low power consumption
    • Typical ICC of 100 nA
    • Typical input leakage current of ±100 nA
  • ±7.8-mA output drive at 6 V
  • Extended ambient temperature range: –40°C to +125°C, TA

The SN74HCS174 contains six positive-edge-triggered D-type flip-flops with shared clock (CLK) and clear (CLR) inputs.

The SN74HCS174 contains six positive-edge-triggered D-type flip-flops with shared clock (CLK) and clear (CLR) inputs.
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Technical documentation

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* Data sheet SN74HCS174 Hex D-Type Flip-Flops with Clear and Schmitt-Trigger Inputs datasheet 28 Sep 2020

Design & development

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Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
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Simulation model

IBIS Model for SN74HCS174, SN74HCS174-Q1

SCLM328.ZIP (249 KB) - IBIS Model
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Package Pins CAD symbols, footprints & 3D models
SOIC (D) 16 Ultra Librarian
TSSOP (PW) 16 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

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