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SN74LV165B-EP

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Enhanced product eight-bit parallel-load shift registers

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Data sheet

SN74LV165B-EP

ACTIVE
Data sheet Order now

Product details

Configuration Parallel-in Bits (#) 8 Technology family LV-A Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Input type Standard CMOS Output type Push-Pull Clock frequency (MHz) 75 IOL (max) (mA) 12 IOH (max) (mA) -12 Supply current (max) (µA) 20 Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -55 to 125 Rating HiRel Enhanced Product
Configuration Parallel-in Bits (#) 8 Technology family LV-A Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Input type Standard CMOS Output type Push-Pull Clock frequency (MHz) 75 IOL (max) (mA) 12 IOH (max) (mA) -12 Supply current (max) (µA) 20 Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -55 to 125 Rating HiRel Enhanced Product
TSSOP (PW) 16 32 mm² 5 x 6.4
  • 2 V to 5.5 V V CC operation
  • Maximum t pd of 10.5 ns at 5 V
  • Supports mixed-mode voltage operation on all ports
  • I off supports partial-power-down mode operation
  • Latch-up performance exceeds 250 mA per JESD 17
  • Operating ambient temperature: -55°C to +125°C
  • Supports defense, aerospace, and medical applications:
    • Controlled baseline
    • One assembly and test site
    • One fabrication site
    • Extended product life cycle
    • Product traceability
  • 2 V to 5.5 V V CC operation
  • Maximum t pd of 10.5 ns at 5 V
  • Supports mixed-mode voltage operation on all ports
  • I off supports partial-power-down mode operation
  • Latch-up performance exceeds 250 mA per JESD 17
  • Operating ambient temperature: -55°C to +125°C
  • Supports defense, aerospace, and medical applications:
    • Controlled baseline
    • One assembly and test site
    • One fabrication site
    • Extended product life cycle
    • Product traceability

The SN74LV165B-EP device is a parallel-load, 8-bit shift registers designed for 2 V to 5.5 V V CC operation.

When the device is clocked, data is shifted toward the serial output Q H. Parallel-in access to each stage is provided by eight individual direct data inputs that are enabled by a low level at the shift/load (SH/ LD) input. The SN74LV165B-EP devices features a clock-inhibit function and a complemented serial output, Q H.

This device is fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

The SN74LV165B-EP device is a parallel-load, 8-bit shift registers designed for 2 V to 5.5 V V CC operation.

When the device is clocked, data is shifted toward the serial output Q H. Parallel-in access to each stage is provided by eight individual direct data inputs that are enabled by a low level at the shift/load (SH/ LD) input. The SN74LV165B-EP devices features a clock-inhibit function and a complemented serial output, Q H.

This device is fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.
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* Data sheet SN74LV165B-EP Enhanced Product, 2-V to 5.5-V, Low-Noise,Parallel-Load 8-Bit Shift Registers datasheet (Rev. A) PDF | HTML 23 Aug 2023

Design & development

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Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
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TSSOP (PW) 16 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

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