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SN74LV6T06-EP

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Enhanced-product, six-bit inverting open-drain fixed-direction level translator

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Data sheet

SN74LV6T06-EP

ACTIVE
Data sheet Order now

Product details

Bits (#) 6 Data rate (max) (Mbps) 6 Topology Open drain Direction control (typ) Fixed-direction Vin (min) (V) 1.6 Vin (max) (V) 5.5 Vout (min) (V) 1.65 Vout (max) (V) 5.5 Applications GPIO Features Over-voltage tolerant inputs, Single supply Prop delay (ns) 12.5 Technology family LVxT Supply current (max) (mA) 0.02 Rating HiRel Enhanced Product Operating temperature range (°C) -55 to 125
Bits (#) 6 Data rate (max) (Mbps) 6 Topology Open drain Direction control (typ) Fixed-direction Vin (min) (V) 1.6 Vin (max) (V) 5.5 Vout (min) (V) 1.65 Vout (max) (V) 5.5 Applications GPIO Features Over-voltage tolerant inputs, Single supply Prop delay (ns) 12.5 Technology family LVxT Supply current (max) (mA) 0.02 Rating HiRel Enhanced Product Operating temperature range (°C) -55 to 125
TSSOP (PW) 14 32 mm² 5 x 6.4
  • Wide operating range of 1.8V to 5.5V

  • Single-supply voltage translator (refer to LVxT Enhanced Input Voltage):

    • Up translation:

      • 1.2V to 1.8V
      • 1.5V to 2.5 V
      • 1.8V to 3.3V
      • 3.3V to 5.0 V

    • Down translation:

      • 5.0V, 3.3V, 2.5 V to 1.8V
      • 5.0V, 3.3V to 2.5V
      • 5.0V to 3.3V
  • 5.5V tolerant input pins
  • Supports standard pinouts
  • Up to 150Mbps with 5V or 3.3V VCC
  • Latch-up performance exceeds 250mAper JESD 17
  • Supports defense, aerospace, and medical applications:
    • Controlled baseline
    • One assembly and test site
    • One fabrication site
    • Extended product life cycle
    • Product traceability
  • Wide operating range of 1.8V to 5.5V

  • Single-supply voltage translator (refer to LVxT Enhanced Input Voltage):

    • Up translation:

      • 1.2V to 1.8V
      • 1.5V to 2.5 V
      • 1.8V to 3.3V
      • 3.3V to 5.0 V

    • Down translation:

      • 5.0V, 3.3V, 2.5 V to 1.8V
      • 5.0V, 3.3V to 2.5V
      • 5.0V to 3.3V
  • 5.5V tolerant input pins
  • Supports standard pinouts
  • Up to 150Mbps with 5V or 3.3V VCC
  • Latch-up performance exceeds 250mAper JESD 17
  • Supports defense, aerospace, and medical applications:
    • Controlled baseline
    • One assembly and test site
    • One fabrication site
    • Extended product life cycle
    • Product traceability

The SN74LV6T06-EP device contains six independent inverters with open-drain outputs and extended voltage operation to allow for level translation. Each inverter performs the Boolean function Y = A in positive logic. The output level is referenced to the supply voltage (VCC) and supports 1.2V, 1.8V, 2.5V, 3.3V, and 5V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2V input to 1.8V output or 1.8V input to 3.3V output). In addition, the 5V tolerant input pins enable down translation (for example, 3.3V to 2.5V output).

The SN74LV6T06-EP device contains six independent inverters with open-drain outputs and extended voltage operation to allow for level translation. Each inverter performs the Boolean function Y = A in positive logic. The output level is referenced to the supply voltage (VCC) and supports 1.2V, 1.8V, 2.5V, 3.3V, and 5V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2V input to 1.8V output or 1.8V input to 3.3V output). In addition, the 5V tolerant input pins enable down translation (for example, 3.3V to 2.5V output).
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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet SN74LV6T06-EP Enhanced Product, Hex Inverter Buffers/Drivers With Open-Drain Outputs datasheet PDF | HTML 22 Jan 2024
* Radiation & reliability report SN74LV6T06-EP Enhanced Product Qualification and Reliability Report PDF | HTML 08 Mar 2024
Application note Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators PDF | HTML 02 Oct 2024
Application note Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 12 Jul 2024
Application note Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 03 Jul 2024

Design & development

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Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
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Package Pins CAD symbols, footprints & 3D models
TSSOP (PW) 14 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

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