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SN74LV6T07

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1.8-V to 5.5-V single power supply 6-bit buffers with tri-state outputs

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Data sheet

SN74LV6T07

ACTIVE
Data sheet Order now

Product details

Bits (#) 6 Data rate (max) (Mbps) 6 Topology Open drain Direction control (typ) Fixed-direction Output drive capability (max) (mA) 8000 Vin (min) (V) 1.65 Vin (max) (V) 5.5 Vout (min) (V) 1.65 Vout (max) (V) 5.5 Applications GPIO Features Overvoltage tolerant inputs, Single supply, Wettable flanks package Technology family LVxT Rating Catalog Operating temperature range (°C) -40 to 85
Bits (#) 6 Data rate (max) (Mbps) 6 Topology Open drain Direction control (typ) Fixed-direction Output drive capability (max) (mA) 8000 Vin (min) (V) 1.65 Vin (max) (V) 5.5 Vout (min) (V) 1.65 Vout (max) (V) 5.5 Applications GPIO Features Overvoltage tolerant inputs, Single supply, Wettable flanks package Technology family LVxT Rating Catalog Operating temperature range (°C) -40 to 85
TSSOP (PW) 14 32 mm² 5 x 6.4 WQFN (BQA) 14 7.5 mm² 3 x 2.5
  • Wide operating range of 1.65 V to 5.5 V
  • 5.5-V tolerant input pins
  • LVxT enhanced inputs combined with open-drain outputs provide maximum voltage translation flexibility:
    • Over 6.67-Mbps operation, (R PU = 1 kΩ, C L = 30 pF)
    • Up translation from 1.2 V to 5 V with 1.8-V supply
    • Down translation from 5 V to 0.8 V or even less with any valid supply
  • 5.5-V tolerant input pins
  • Supports standard function pinout
  • Latch-up performance exceeds 250 mA per JESD 17
  • Wide operating range of 1.65 V to 5.5 V
  • 5.5-V tolerant input pins
  • LVxT enhanced inputs combined with open-drain outputs provide maximum voltage translation flexibility:
    • Over 6.67-Mbps operation, (R PU = 1 kΩ, C L = 30 pF)
    • Up translation from 1.2 V to 5 V with 1.8-V supply
    • Down translation from 5 V to 0.8 V or even less with any valid supply
  • 5.5-V tolerant input pins
  • Supports standard function pinout
  • Latch-up performance exceeds 250 mA per JESD 17

The SN74LV6T07 device contains six independent buffers with open-drain outputs. Each buffer performs the Boolean function Y = A in positive logic.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output).

The SN74LV6T07 device contains six independent buffers with open-drain outputs. Each buffer performs the Boolean function Y = A in positive logic.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output).
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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet SN74LV6T07 Hex Open-Drain Buffers with Integrated Translation datasheet PDF | HTML 21 Aug 2023
Application note Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 12 Jul 2024
Application note Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 03 Jul 2024
Application brief Enabling Modular PLC System Designs with Single-Supply Level Translation PDF | HTML 16 Apr 2024

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
Not available on TI.com
Package Pins CAD symbols, footprints & 3D models
TSSOP (PW) 14 Ultra Librarian
WQFN (BQA) 14 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

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