Single-supply voltage translator (refer to LVxT Enhanced Input Voltage):
Up translation:
1.2V to 1.8V
1.5V to 2.5V
1.8V to 3.3V
3.3V to 5.0V
Down translation:
The SN74LV6T17-EP device contains six independent Buffers with Schmitt-trigger inputs. Each gate performs the Boolean function Y = A in positive logic. The output level is referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels.
The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2V input to 1.8V output or 1.8V input to 3.3V output). In addition, the 5V tolerant input pins enable down translation (for example, 3.3V to 2.5V output).
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | SN74LV6T17-EP Enhanced Product, Hex Schmitt-Trigger Buffer with Integrated Translation datasheet | PDF | HTML | 22 Jan 2024 |
| Application note | Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators | PDF | HTML | 02 Oct 2024 | |
| Application note | Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators | PDF | HTML | 12 Jul 2024 | |
| Application note | Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) | PDF | HTML | 03 Jul 2024 |
For additional terms or required resources, click any title below to view the detail page where available.
The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| TSSOP (PW) | 14 | Ultra Librarian |
Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.
If you have questions about quality, packaging or ordering TI products, see TI support.