Down translation:
The SN74LV8T594 device contains an 8-bit, serial-in, parallel-out shift register. Each parallel output of the shift register is fed through a storage register before reaching the primary device outputs (QA through QH). Separate clocks (SRCLK and RCLK) and direct overriding clear (SRCLR and RCLR) inputs are provided for both the shift and storage registers, allowing for loading data separately from sending it to the outputs. Additionally, the last output of the internal shift register is sent directly to the output QH’ providing a method to daisy-chain multiple shift registers.
The input is designed with a reduced threshold circuit to support up translation when the supply voltage is larger than the input voltage. Additionally, the 5V tolerant input pins enable down translation when the input voltage is larger than the supply voltage. The output level is always referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels.
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | SN74LV8T594 Octal Shift Register with Output Registers datasheet | PDF | HTML | 27 Feb 2024 |
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The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,
14-24-NL-LOGIC-EVM is a flexible evaluation module (EVM) designed to support any logic or translation device that has a 14-pin to 24-pin BQA, BQB, RGY, RSV, RJW or RHL package.
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| TSSOP (PW) | 16 | Ultra Librarian |
| WQFN (BQB) | 16 | Ultra Librarian |
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