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SN74LVC240A

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8-ch, 1.65-V to 3.6-V inverters with 3-state outputs

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Data sheet

SN74LVC240A

ACTIVE
Data sheet Order now

Product details

Technology family LVC Number of channels 8 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (µA) 10 Input type Standard CMOS Output type 3-State Features Balanced outputs, Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 125
Technology family LVC Number of channels 8 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (µA) 10 Input type Standard CMOS Output type 3-State Features Balanced outputs, Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 125
SOIC (DW) 20 131.84 mm² (12.8 mm × 10.3 mm) TVSOP (DGV) 20 32 mm² (5 mm × 6.4 mm) TSSOP (PW) 20 41.6 mm² (6.5 mm × 6.4 mm) SSOP (DB) 20 56.16 mm² (7.2 mm × 7.8 mm) SOP (NS) 20 98.28 mm² (12.6 mm × 7.8 mm) VSSOP (DGS) 20 24.99 mm² (5.1 mm × 4.9 mm)
  • Operates from 1.65V to 3.6V
  • Inputs accept voltages to 5.5V
  • Maximum tpd of 6.5ns at 3.3V
  • Typical VOLP (output ground bounce) <0.8V at VCC = 3.3V, TA = 25°C
  • Typical VOHV (output VOH undershoot) >2V at VCC = 3.3V, TA = 25°C
  • Supports mixed-mode signal operation on all ports (5V input/output voltage with 3.3V VCC)
  • Ioff supports live insertion, partial-power-down mode, and back-drive protection
  • Latch-up performance exceeds 100mA per JESD 17
  • Operates from 1.65V to 3.6V
  • Inputs accept voltages to 5.5V
  • Maximum tpd of 6.5ns at 3.3V
  • Typical VOLP (output ground bounce) <0.8V at VCC = 3.3V, TA = 25°C
  • Typical VOHV (output VOH undershoot) >2V at VCC = 3.3V, TA = 25°C
  • Supports mixed-mode signal operation on all ports (5V input/output voltage with 3.3V VCC)
  • Ioff supports live insertion, partial-power-down mode, and back-drive protection
  • Latch-up performance exceeds 100mA per JESD 17

The SN74LVC240A is an octal buffer with 3-state outputs. The device is configured into two banks of four drivers, each controlled by an output enable pin.

The SN74LVC240A is an octal buffer with 3-state outputs. The device is configured into two banks of four drivers, each controlled by an output enable pin.
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Technical documentation

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* Data sheet SN74LVC240A Octal Buffer/Driver with 3-State Outputs datasheet (Rev. M) PDF | HTML Jun 25, 2026

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
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Evaluation board

14-24-NL-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin non-leaded packages

14-24-NL-LOGIC-EVM is a flexible evaluation module (EVM) designed to support any logic or translation device that has a 14-pin to 24-pin BQA, BQB, RGY, RSV, RJW or RHL package.

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Simulation model

SN74LVC240A Behavioral SPICE Model

SCAM103.ZIP (7 KB) - PSpice model
Supported products & hardware
Simulation model

SN74LVC240A IBIS Model

SCAM041.ZIP (40 KB) - IBIS model
Supported products & hardware
Package Pins CAD symbols, footprints & 3D models
SOIC (DW) 20 Ultra Librarian
TVSOP (DGV) 20 Ultra Librarian
TSSOP (PW) 20 Ultra Librarian
SSOP (DB) 20 Ultra Librarian
SOP (NS) 20 Ultra Librarian
VSSOP (DGS) 20 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

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