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SN74LVCH8T245

ACTIVE

8-bit dual-supply bus transceiver with configurable voltage translation and 3-state outputs

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Data sheet

SN74LVCH8T245

ACTIVE
Data sheet Order now

Product details

Bits (#) 8 Data rate (max) (Mbps) 200 Topology Push-Pull Vout (min) (V) 1.65 Vout (max) (V) 5.5 Features Bus-hold, Output enable, Overvoltage tolerant inputs, Partial power down (Ioff), Vcc isolation Prop delay (ns) 6.5 Technology family LVC Supply current (max) (mA) 0.025 Rating Catalog Operating temperature range (°C) -40 to 85
Bits (#) 8 Data rate (max) (Mbps) 200 Topology Push-Pull Vout (min) (V) 1.65 Vout (max) (V) 5.5 Features Bus-hold, Output enable, Overvoltage tolerant inputs, Partial power down (Ioff), Vcc isolation Prop delay (ns) 6.5 Technology family LVC Supply current (max) (mA) 0.025 Rating Catalog Operating temperature range (°C) -40 to 85
SSOP (DB) 24 63.96 mm² 8.2 x 7.8 TSSOP (PW) 24 49.92 mm² 7.8 x 6.4 TVSOP (DGV) 24 32 mm² 5 x 6.4 VQFN (RHL) 24 19.25 mm² 5.5 x 3.5
  • Fully configurable dual-rail design
  • Robust, glitch-free power supply sequencing
  • Control inputs (DIR and OE) VIH and VIL levels are referenced to VCCA
  • Bus hold on data inputs eliminates the need for external pullup and pulldown resistors
  • VCC isolation feature and VCC disconnect feature
    • if either VCC input is below 100mV or left floating, all I/O outputs are disabled and become high- impedance state
  • Ioff supports Partial-Power-Down node operation
  • Latch-up performance exceeds 100mA per JESD 78, class II
  • ESD protection exceeds JESD 22
  • Fully configurable dual-rail design
  • Robust, glitch-free power supply sequencing
  • Control inputs (DIR and OE) VIH and VIL levels are referenced to VCCA
  • Bus hold on data inputs eliminates the need for external pullup and pulldown resistors
  • VCC isolation feature and VCC disconnect feature
    • if either VCC input is below 100mV or left floating, all I/O outputs are disabled and become high- impedance state
  • Ioff supports Partial-Power-Down node operation
  • Latch-up performance exceeds 100mA per JESD 78, class II
  • ESD protection exceeds JESD 22

The SN74LVCH8T245 is an 8-bit noninverting bus transceiver that uses two separate configurable power-supply rails. The A port is designed to track VCCA, which accepts any supply voltage from 1.65V to 5.5V. The B port is designed to track VCCB, which also accepts any supply voltage from 1.65V to 5.5V. This allows for universal low-voltage bidirectional translation between any of the 1.8V, 2.5V, 3.3V, and 5.5V voltage nodes.

The SN74LVCH8T245 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs, the A-port outputs, or place both output ports into a high-impedance state. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports are always active.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device. The VCC isolation feature is designed so that if either VCCA or VCCB is at GND, then the outputs are in the high-impedance state. To put the device in the high-impedance state during power up or power down, tie OE to VCCA through a pullup resistor; the current-sinking capability of the driver determines the minimum value of the resistor.

The SN74LVCH8T245 is designed so that the control pins (DIR and OE) are referenced to VCCA.

The SN74LVCH8T245 is an 8-bit noninverting bus transceiver that uses two separate configurable power-supply rails. The A port is designed to track VCCA, which accepts any supply voltage from 1.65V to 5.5V. The B port is designed to track VCCB, which also accepts any supply voltage from 1.65V to 5.5V. This allows for universal low-voltage bidirectional translation between any of the 1.8V, 2.5V, 3.3V, and 5.5V voltage nodes.

The SN74LVCH8T245 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs, the A-port outputs, or place both output ports into a high-impedance state. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports are always active.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device. The VCC isolation feature is designed so that if either VCCA or VCCB is at GND, then the outputs are in the high-impedance state. To put the device in the high-impedance state during power up or power down, tie OE to VCCA through a pullup resistor; the current-sinking capability of the driver determines the minimum value of the resistor.

The SN74LVCH8T245 is designed so that the control pins (DIR and OE) are referenced to VCCA.
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Technical documentation

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* Data sheet SN74LVCH8T245 8-BIT Dual-Supply Bus Transceiver With Configurable Level-Shifting, Voltage Translation, and 3-State Outputs datasheet (Rev. D) PDF | HTML 29 May 2026
Selection guide Logic Guide (Rev. AC) PDF | HTML 13 Nov 2025
Application note Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators PDF | HTML 02 Oct 2024
Application note Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 12 Jul 2024
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Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
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Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
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User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
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User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 18 Dec 2002
Application note Texas Instruments Little Logic Application Report 01 Nov 2002
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Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 Dec 1997
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Design & development

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Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
Not available on TI.com
Evaluation board

14-24-NL-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin non-leaded packages

14-24-NL-LOGIC-EVM is a flexible evaluation module (EVM) designed to support any logic or translation device that has a 14-pin to 24-pin BQA, BQB, RGY, RSV, RJW or RHL package.

User guide: PDF | HTML
Not available on TI.com
Evaluation board

AVCLVCDIRCNTRL-EVM — Generic EVM for Direction-Controlled Bidirectional Translation Device Supporting AVC and LVC

The generic EVM is designed to support one, two, four and eight channel LVC and AVC direction-controlled translation devices. It also supports the bus hold and automotive -Q1 devices in the same number of channels. The AVC are low voltage translation devices with lower drive strength of 12mA. LVC (...)

User guide: PDF
Not available on TI.com
Simulation model

SN74LVCH8T245 IBIS Model

SCEM493.ZIP (55 KB) - IBIS Model
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Package Pins CAD symbols, footprints & 3D models
SSOP (DB) 24 Ultra Librarian
TSSOP (PW) 24 Ultra Librarian
TVSOP (DGV) 24 Ultra Librarian
VQFN (RHL) 24 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

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