Home Logic & voltage translation Voltage translators & level shifters Ground-level translators
Home
Logic & voltage translation
Voltage translators & level shifters
Ground-level translators
NEW

TXG8020

PREVIEW

±80V, 2-bit fixed direction ground level translators, 2/0 configuration

Order now
Data sheet

TXG8020

PREVIEW
Data sheet Order now

Product details

Rating Catalog Ground offset voltage (max) (V) 80 Bits (#) 2 Topology Push-Pull Applications GPIO Forward/reverse channels 2 forward / 0 reverse Isolation rating Functional Data rate (max) (Mbps) 250 Prop delay (ns) 5.9 CMTI (V/µs) 250 Technology family TXG Vin (min) (V) 1.71 Vin (max) (V) 5.5 Vout (min) (V) 1.71 Vout (max) (V) 5.5 Current consumption per channel (1 Mbps) (typ) (mA) 3.3 Features Partial power down (Ioff)
Rating Catalog Ground offset voltage (max) (V) 80 Bits (#) 2 Topology Push-Pull Applications GPIO Forward/reverse channels 2 forward / 0 reverse Isolation rating Functional Data rate (max) (Mbps) 250 Prop delay (ns) 5.9 CMTI (V/µs) 250 Technology family TXG Vin (min) (V) 1.71 Vin (max) (V) 5.5 Vout (min) (V) 1.71 Vout (max) (V) 5.5 Current consumption per channel (1 Mbps) (typ) (mA) 3.3 Features Partial power down (Ioff)
SOIC (D) 8 29.4 mm² 4.9 x 6
  • Supports DC shifts up to ±80V
  • AC Noise Rejection of 140VPP up to 1MHz
  • CMTI of 250V/µs
  • Low Prop Delay (<5ns) and Ch-Ch Skew (<0.20ns)
  • Greater than 250Mbps
  • Low power consumption (0.8mA per channel at 1Mbps, 1.8V)
  • Fully configurable dual-rail design allows each port to operate from 1.71V to 5.5V
  • 4, 2, 1 channel devices with multiple configurations will be available
  • Two device variants:
    • TXG8020: 2 forward
    • TXG8021: 1 forward, 1 reverse
  • Supports VCC disconnect feature (I/Os are forced into high-Z)
  • Schmitt-trigger inputs allows for slow and noisy signals
  • Inputs with integrated static pull-down resistors prevent channels from floating
  • Operating temperature from –40°C to +125°C
  • Latch-up performance exceeds 100mA per JESD 78, class II
    • ESD protection exceeds JESD 22
    • 2500V human-body model
    • 500V charged-device model
  • Package options provided:
    • DSG (WSON-8)
    • DDF (SOT-8)
    • D (SOIC-8)
  • Supports DC shifts up to ±80V
  • AC Noise Rejection of 140VPP up to 1MHz
  • CMTI of 250V/µs
  • Low Prop Delay (<5ns) and Ch-Ch Skew (<0.20ns)
  • Greater than 250Mbps
  • Low power consumption (0.8mA per channel at 1Mbps, 1.8V)
  • Fully configurable dual-rail design allows each port to operate from 1.71V to 5.5V
  • 4, 2, 1 channel devices with multiple configurations will be available
  • Two device variants:
    • TXG8020: 2 forward
    • TXG8021: 1 forward, 1 reverse
  • Supports VCC disconnect feature (I/Os are forced into high-Z)
  • Schmitt-trigger inputs allows for slow and noisy signals
  • Inputs with integrated static pull-down resistors prevent channels from floating
  • Operating temperature from –40°C to +125°C
  • Latch-up performance exceeds 100mA per JESD 78, class II
    • ESD protection exceeds JESD 22
    • 2500V human-body model
    • 500V charged-device model
  • Package options provided:
    • DSG (WSON-8)
    • DDF (SOT-8)
    • D (SOIC-8)

The TXG802x is a 2-bit, fixed direction, non-galvanic based voltage and ground-level translator that can support both logic-level shifting between 1.71V to 5.5V and ground-level shifting up to ±80V. Compared to traditional level shifters, the TXG802x family can solve the challenges of voltage translation across different ground levels. The Simplified Diagram shows a common use case where DC shift occurs between GNDA to GNDB due to parasitic resistance or capacitance.

VCCA is referenced to GNDA and VCCB is referenced to GNDB. Ax pins are referenced to VCCA logic level while Bx pins are referenced to VCCB logic levels. Both A port and B port can accept voltages from 1.71V to 5.5V. The leakage between GNDA and GNDB is <2µA when VCC to GND is shorted.

The TXG802x device helps improve noise immunity and power sequencing across different ground domains while providing low power consumption, latency and channel-to-channel skew. It can supress noise levels of 140VPP up to 1MHz (Figure 7-4). This device can support multiple interfaces such as UART, GPIO, and JTAG.

The TXG802x is a 2-bit, fixed direction, non-galvanic based voltage and ground-level translator that can support both logic-level shifting between 1.71V to 5.5V and ground-level shifting up to ±80V. Compared to traditional level shifters, the TXG802x family can solve the challenges of voltage translation across different ground levels. The Simplified Diagram shows a common use case where DC shift occurs between GNDA to GNDB due to parasitic resistance or capacitance.

VCCA is referenced to GNDA and VCCB is referenced to GNDB. Ax pins are referenced to VCCA logic level while Bx pins are referenced to VCCB logic levels. Both A port and B port can accept voltages from 1.71V to 5.5V. The leakage between GNDA and GNDB is <2µA when VCC to GND is shorted.

The TXG802x device helps improve noise immunity and power sequencing across different ground domains while providing low power consumption, latency and channel-to-channel skew. It can supress noise levels of 140VPP up to 1MHz (Figure 7-4). This device can support multiple interfaces such as UART, GPIO, and JTAG.
filter Find other Ground-level translators
Download View video with transcript Video

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 2
Top documentation Type Title Format options Date
* Data sheet TXG802x 2-bit , ± 80V Ground-Level Translator datasheet PDF | HTML 17 Jun 2025
Application brief Top Questions about Ground-Level Translators PDF | HTML 27 May 2026

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
Not available on TI.com
Package Pins CAD symbols, footprints & 3D models
SOIC (D) 8 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

Support & training

TI E2E™ forums with technical support from TI engineers

View all forum topics

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos