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SN54AS821A

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具有三态输出的 10 位总线接口触发器

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数据表

SN54AS821A

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产品详情

Number of channels 10 Technology family AS Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type Bipolar Output type 3-State Clock frequency (max) (MHz) 125 IOL (max) (mA) 48 IOH (max) (mA) -24 Supply current (max) (µA) 113000 Features High speed (tpd 10-50ns) Operating temperature range (°C) -55 to 125 Rating Military
Number of channels 10 Technology family AS Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type Bipolar Output type 3-State Clock frequency (max) (MHz) 125 IOL (max) (mA) 48 IOH (max) (mA) -24 Supply current (max) (µA) 113000 Features High speed (tpd 10-50ns) Operating temperature range (°C) -55 to 125 Rating Military
CDIP (JT) 24 221.44 mm² 32 x 6.92
  • Functionally Equivalent to AMD's AM29821
  • Provide Extra Data Width Necessary for Wider Address/Data Paths or Buses With Parity
  • Outputs Have Undershoot-Protection Circuitry
  • Power-Up High-Impedance State
  • Buffered Control Inputs to Reduce
    dc Loading Effects
  • Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs

 
  • Functionally Equivalent to AMD's AM29821
  • Provide Extra Data Width Necessary for Wider Address/Data Paths or Buses With Parity
  • Outputs Have Undershoot-Protection Circuitry
  • Power-Up High-Impedance State
  • Buffered Control Inputs to Reduce
    dc Loading Effects
  • Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs

 

These 10-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.

The ten flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are true to the data (D) input.

A buffered output-enable () input can be used to place the ten outputs in either a normal logic state (high or low logic levels) or a high-
impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

does not affect the internal operation of the flip-flops. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state.

The SN54AS821A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74AS821A is characterized for operation from 0°C to 70°C.

 

 

These 10-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.

The ten flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are true to the data (D) input.

A buffered output-enable () input can be used to place the ten outputs in either a normal logic state (high or low logic levels) or a high-
impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

does not affect the internal operation of the flip-flops. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state.

The SN54AS821A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74AS821A is characterized for operation from 0°C to 70°C.

 

 
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类型 标题 下载最新的英语版本 日期
* 数据表 10-Bit Bus Interface Flip-Flops With 3-State Outputs 数据表 (Rev. A) 1995年 8月 1日
* SMD SN54AS821A SMD 5962-90780 2016年 6月 21日
应用手册 Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022年 12月 15日
选择指南 Logic Guide (Rev. AB) 2017年 6月 12日
应用手册 Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
选择指南 逻辑器件指南 2014 (Rev. AA) 最新英语版本 (Rev.AB) 2014年 11月 17日
用户指南 LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
应用手册 Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
应用手册 TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
应用手册 使用逻辑器件进行设计 (Rev. C) 1997年 6月 1日
应用手册 Advanced Schottky Load Management 1997年 2月 1日
应用手册 Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
应用手册 Live Insertion 1996年 10月 1日
应用手册 Advanced Schottky (ALS and AS) Logic Families 1995年 8月 1日

设计和开发

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封装 引脚 CAD 符号、封装和 3D 模型
CDIP (JT) 24 Ultra Librarian
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订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

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