JESD204B links are the latest trend in data-converter digital interfaces. These links take advantage of high-speed serial-digital technology to offer many compelling benefits including improved channel densities. This reference design addresses one of the challenges of adopting the new interface: understanding and designing the link latency. An example achieves deterministic latency and determines the link latency of a system containing the Texas Instruments LM97937 ADC and Xilinx Kintex 7 FPGA.
A fully assembled board has been developed for testing and performance validation only, and is not available for sale.
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Reference design overview and verified performance test data
Test results for the reference design, including efficiency graphs, test prerequisites and more
Detailed schematic diagram for design layout and components
Complete listing of design components, reference designators, and manufacturers/part numbers
Design file that contains information on physical board layer of design PCB
Includes TI products in the design and potential alternatives.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Design guide | JESD204B Link Latency Using a High-Speed ADC and FPGA Design Guide | Feb. 18, 2014 | |
| Test report | TIDA-00153 Test Results | Feb. 19, 2014 |
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