The increasing demand on wireless networks to provide faster data links to customers has driven transceiver hardware to increasingly demanding performance with enough bandwidth to support the largest standardized multi-carrier frequency bands (with band aggregation in some cases) and enough receiver sensitivity and dynamic range to function in the presence of the strong blocking signals common in busy environments. This reference design describes a radio frequency (RF) receiver reference design with 16-bit sampler that achieves more than 100 MHz of bandwidth including a down-converting mixer, digital variable gain amplifier (DVGA), high speed pipelined analog-to-digital converter (ADC), local oscillator (LO) RF synthesizer and jitter-cleaning clock generator.
A fully assembled board has been developed for testing and performance validation only, and is not available for sale.
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Reference design overview and verified performance test data
Detailed schematic diagram for design layout and components
Complete listing of design components, reference designators, and manufacturers/part numbers
Detailed overview of design layout for component placement
Detailed overview of design layout for component placement
Files used for 3D models or 2D drawings of IC components
Design file that contains information on physical board layer of design PCB
PCB layer plot file used for generating PCB design layout
Includes TI products in the design and potential alternatives.
| Type | Title | Date | ||
|---|---|---|---|---|
| Technical article | How to select a power-efficient narrowband receiver for active antenna-array syste | PDF | HTML | Apr. 12, 2016 | |
| User guide | TIDA-00360 Performance Summary | Mar. 17, 2015 | ||
| Design guide | 700–2700-MHz Dual-Channel Receiver With 16-Bit ADC and 100 MHz of IF Bandwidth | Feb. 06, 2015 |
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