CDC-CDCM7005-CALC
CDC7005 和 CDCM7005 PLL 环路带宽计算器
CDC-CDCM7005-CALC
概述
This tool helps to determine the right divider values (M, N & P) and to choose the filter type and components. This calculator will help to find out the appropriate loop bandwidth, phase margin, jitter peaking, etc. just varying the loop parameters like PFD frequency, filter components, Charge pump current, and VCO gain (Hz/V). This is a software package that lets the Engineers enter a piecewise-linear noise model for the VCO (VCXO) and the reference clock source to predict the PLL output phase noise and hence calculate the phase jitter.
特性
The lab view based tool can:
- Determine the PFD frequency automatically
- Calculate loop bandwidth, Phase margin and Jitter peaking
- Predict the PLL output Phase noise
- Calculate Phase Jitter (rms)
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| 类型 | 标题 | 下载最新的英语版本 | 日期 | |||
|---|---|---|---|---|---|---|
| 数据表 | CDCM7005-SP 3.3-V High Performance Rad-Tolerant Class V, Clock Synchronizer and Jitter Cleaner 数据表 (Rev. G) | PDF | HTML | 2015-12-3 |