LMK04832SEPEVM
LMK04832-SEP 超低噪声 3.2GHz、15 路输出时钟抖动清除器评估模块
LMK04832SEPEVM
概述
LMK04832-SEP 评估模块 (EVM) 是一个用于评估 LMK04832-SEP 性能和特性的平台。LMK04832-SEP 是一款符合 JESD204B/C 标准的航天级、超低噪声、双环路时钟抖动清除器。
每个 EVM 上的 LMK04832-SEP 器件均为工程模型,仅适用于工程评估。该器件和 EVM 不适合
鉴定、量产、辐射测试或飞行用途。
特性
- 单粒子闩锁 (SEL) 和单粒子功能中断 (SEFI) 抗扰度 > 43 MeV.cm2/mg
- 提供 JESD204B/C 支持,适用于需要系统基准 (SYSREF) 的航天应用
- 6GHz 外部压控振荡器 (VCO) 或分配输入
- 多模式
- 双锁相环 (PLL)
- 单个 PLL
- 时钟分配
- 适用于双环路时钟抖动清除器的完整电路,已经过性能优化和测试
时钟抖动清除器
立即订购并开发
LMK04832SEPEVM — LMK04832-SEP evaluation module for ultra-low-noise, 3.2-GHz, 15-output, clock jitter cleaner
TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices
TICS Pro 1.7.7.9 installer binary for Windows operating system
产品
时钟发生器
时钟缓冲器
振荡器
时钟抖动清除器
时钟网络同步器
射频 PLL 与合成器
硬件开发
评估板
文档
TICS Pro 1.7.7.9 Release Notes
TICS Pro 1.7.7.9 Software Manifest
发布信息
NOTE: v1.7.7.8 was withdrawn due to the installer being built with an older version of several profiles. v1.7.7.9 includes the correct files, and is otherwise identical to v1.7.7.8.
Bug Fixes
- Start Page: dimming improvements for unused input references, force FB config 1 only and require manual copying for FB config 2
- Validation Page: DPLL LOFL validation registers for FB2 are programmed for cases where FB2 is used
- ZDM Page: Added relative time calculations for DPLLx_PH_OFFSET
- Programming Page: Added DPLL loop filter register generator, clearly indicate ROM-only registers for post-EEPROM boot sequence
- LMK5B12212 will now calculate loop filter values
- LMK5B12212 and LMK5C12212A "Read Status" and "Read RO Regs" buttons fixed
- LMK5B12212 and LMK5C12212A corrected PLL1 VCO post-divider frequency on OUT0&1, OUT2&3 pages
- Improved accuracy of frequency error warnings
- Frequency Planner: OUT0/OUT1 CMOS and LDO voltage are now correctly set, REFx for OUT0 or OUT1 is now correctly set
- ZDM configuration now fails more gracefully for unsupported non-integer input/output attempts
Known Issues
- NEW: LMK5B and LMK5C family - In some cases, "Assign Selected VCO Settings to Device" and "Apply Output Clock Settings to Device" may need to be pressed twice for certain cascaded configurations to display correctly
- LMK5C33216 - When cascading from VCO3 to DPLL input, the divide value must manually be entered into DPLLx_REF5_RDIV as ( VCO3 output frequency / DPLLx TDC frequency )
- LMK05318 - In some cases, it is necessary to press "Calculate Frequency Plan" twice for correct VCO2 frequency. This issue is resolved in LMK05318B GUI.
- Burst mode page looping requires long delays to halt, and halting may crash the GUI. If possible, do not loop in burst mode.
- User Controls page can sometimes become desynchronized from Raw Registers and other pages. Refer to Raw Registers or other pages for correct values. Saving/Loading and Import/Export of register data is unaffected, and register data will still be written to and read from connected devices correctly.
技术文档
类型 | 标题 | 下载最新的英文版本 | 日期 | |||
---|---|---|---|---|---|---|
* | EVM 用户指南 | LMK04832SEPEVM User’s Guide | PDF | HTML | 2022年 9月 28日 | ||
证书 | LMK04832SEPEVM EU RoHS Declaration of Conformity (DoC) | 2022年 9月 6日 |