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  • ADC3908Dx and ADC3908Sx 8-bit, 25 to 125MSPS Low Latency, Low Power, Small, Single and Dual Channel ADC with Integrated Input Buffers

    • SBASAU9 October   2024 ADC3908D025 , ADC3908D065 , ADC3908D125 , ADC3908S025 , ADC3908S065 , ADC3908S125

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  • ADC3908Dx and ADC3908Sx 8-bit, 25 to 125MSPS Low Latency, Low Power, Small, Single and Dual Channel ADC with Integrated Input Buffers
  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - AC Specifications (25 MSPS)
    8. 6.8  Electrical Characteristics - AC Specifications (65 MSPS)
    9. 6.9  Electrical Characteristics - AC Specifications (125 MSPS)
    10. 6.10 Timing Requirements
    11. 6.11 Output Interface Timing Diagram
    12. 6.12 Typical Characteristics: 25MSPS
    13. 6.13 Typical Characteristics - 65MSPS
    14. 6.14 Typical Characteristics - 125MSPS
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
        1. 7.3.1.1 Single Ended Input
        2. 7.3.1.2 Differential Input
        3. 7.3.1.3 Analog Input Bandwidth
      2. 7.3.2 Sampling Clock Input
      3. 7.3.3 Digital Interface
        1. 7.3.3.1 Test Pattern
        2. 7.3.3.2 Interface Configuration using Pin Control
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Power Down
  9. 8 Application Information Disclaimer
    1. 8.1 Typical Application
      1. 8.1.1 Design Requirements
      2. 8.1.2 Detailed Design Procedure
        1. 8.1.2.1 Input Signal Path
        2. 8.1.2.2 Sampling Clock
      3. 8.1.3 Application Curves
    2. 8.2 Initialization Set Up
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
  13. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • RSM|32
    • MPQF195B
Thermal pad, mechanical data (Package|Pins)
  • RSM|32
    • QFND112H
Orderable Information
  • sbasau9_oa
  • sbasau9_pm
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Data Sheet

ADC3908Dx and ADC3908Sx 8-bit, 25 to 125MSPS Low Latency, Low Power, Small, Single and Dual Channel ADC with Integrated Input Buffers

1 Features

  • Sampling rate up to 125MSPS
  • Latency: 1 clock cycle
  • Low power (2 channel):
    • 90mW at 125MSPS
    • 56mW at 25MSPS
    • 3mW in PD mode
  • Small footprint: 32-VQFN (4mm x 4mm)
  • Single or dual channel ADC
  • Internal reference
  • No missing codes, ±0.25 LSB INL
  • Buffered, differential or single ended inputs
  • Input bandwidth: 150MHz (3dB)
  • Single 1.8V supply
    • Optional 3.3VIO capability
  • Industrial temperature range: -40°C to 105°C
  • Parallel (SDR, DDR) CMOS interface
  • Spectral performance (FSCLK = 125MSPS, fIN = 5 MHz):
    • SNR: 49.8dBFS
    • SFDR: 60dBFS

2 Applications

  • Low latency control loops
  • Laser scanners

  • Displacement sensors

  • Detection equipment

3 Description

The ADC3908Dx and ADC3908Sx are a family of ultra-low power 8-bit 125MSPS high-speed dual and single channel analog-to-digital converters. High-speed control loops benefit from the short latency of only 1 clock cycle. The ADC consumes only 90mW at 125MSPS with a power consumption that scales with lower sampling rates.

The ADC3908Dx and ADC3908Sx uses parallel DDR or SDR CMOS interface to output the data, and can be driven at +1.8V or +3.3V to accommodate various receiver requirements. The analog input and output interface can be easily configured via pin control (Interface Configuration Table). The device is a pin-to-pin compatible family of ADCs with 8 and 10-bit resolution and different speed grades. The device is available in a 32-pin VQFN package, and supports industrial temperature range from -40 to +105°C.

Package Information
PART NUMBERPACKAGE(1)PACKAGE SIZE(2)
ADC3908D025, 'D065, 'D125 ADC3908S025,'S065, 'S125VQFN (32)4mm × 4mm
(1) For more information, see Section 11.
(2) The package size (length × width) is a nominal value and includes pins, where applicable.
Device Information
PART NUMBER
(c= #CH; sss= MSPS)		RESOLUTIONSAMPLING RATE MSPS
ADC3910csss 10-Bit 25, 65, 125
ADC3908csss8-Bit25, 65, 125
ADC3908D025 ADC3908D065 ADC3908D125 ADC3908S025 ADC3908S065 ADC3908S125 Block Diagram Block Diagram

4 Device Comparison

Table 4-1 Device Comparison Table
Device Resolution (Bits) Channels Sample Rate (MSPS) Control Interface Digital Features
ADC3910D125 10 2 125 SPI Control Full Features
ADC3910S125 10 1 125 SPI Control Full Features
ADC3910D065 10 2 65 SPI Control Full Features
ADC3910S065 10 1 65 SPI Control Full Features
ADC3910D025 10 2 25 SPI Control Full Features
ADC3910S025 10 1 25 SPI Control Full Features
ADC3908D125 8 2 125 Pin Control Not available
ADC3908S125 8 1 125 Pin Control Not available
ADC3908D065 8 2 65 Pin Control Not available
ADC3908S065 8 1 65 Pin Control Not available
ADC3908D025 8 2 25 Pin Control Not available
ADC3908S025 8 1 25 Pin Control Not available

5 Pin Configuration and Functions

A. AGND is soldered to the thermal pad
Figure 5-1 RSM (VQFN) Package, 32-Pin (Top View)
Table 5-1 Pin Functions
PINTYPEDESCRIPTION
NAMENO.
INPUT or REFERENCE
INAP10IPositive analog input, channel A
INAM11INegative analog input, channel A
INBP/NC14IPositive analog input, channel B (NC on single channel device)
INBM/NC15INegative analog input, channel B (NC on single channel device)
VCM7OCommon-mode voltage output for the analog inputs, 1.25 V
CLOCK
CLK8ISampling clock input for the ADC
CONFIGURATION
RESET9IHardware reset. Active high. This pin has an internal 60 kΩ pull-down resistor.
M016IDefault, internal 40 kΩ pull-down resistor.

Tie to GND for dual channel devices or AVDD for single channel devices.

This pin is used to configure default operating conditions. Interface configuration table

M118IDefault, internal 40 kΩ pull-down resistor.

This pin is used to configure default operating conditions. Interface configuration table

M219IDefault, internal 40 kΩ pull-down resistor.

This pin is used to configure default operating conditions. Interface configuration table

DIGITAL INTERFACE
D032OParallel CMOS digital lane output data.
D131O
D226O
D325O
D424O
D523O
D622O
D721O
DCLK30OCMOS output for data bit clock.
DCLK29OInverse data bit clock for CMOS output data.
PDN6IDefault, pin has 60 kΩ pull-down. When PDN is pulled high device is put in a powerdown state.
POWER SUPPLY
AVDD12, 13IAnalog 1.8 V power supply
GNDPowerPAD™IAnalog Ground, 0 V
IOVDD27I1.8 V power supply for digital interface
DGND5, 28IGround, 0 V for digital interface
OTHER
NC 1, 2, 3, 4, 5, 17, 20 - No connection. Connect to ground.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN MAX UNIT
Supply voltage range 1.8 V, AVDD –0.3 2.1 V
Supply voltage range 1.8 V to 3.3 V, IOVDD –0.3 3.6
Supply voltage range, GND, DGND –0.3 0.3
Voltage applied to input pins INAP/M, INBP/M, CLK –0.3 2.1
RESET, PDN, M0 , M1, M2 –0.3 2.1
Junction temperature, TJ 125 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) 1000 V
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all pins(2) 500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Supply voltage range  Supply voltage range 1.8v AVDD(1) 1.7 1.8 1.9 V
Supply voltage range  IOVDD(1) 1.7 1.8 1.9 V
Supply voltage range  Supply voltage range 3.3v IOVDD(1) 3.2 3.3 3.4 V
TA Operating free-air temperature –40 105 °C
TJ Operating junction temperature 115(2) °C
(1) Measured to GND.
(2) Prolonged use above this junction temperature may increase the device failure-in-time (FIT) rate.

6.4 Thermal Information

THERMAL METRIC(1) ADC39xx UNIT
RSM (QFN)
32 Pins
RΘJA Junction-to-ambient thermal resistance 38.1 °C/W
RΘJC(top) Junction-to-case (top) thermal resistance 37.2 °C/W
RΘJB Junction-to-board thermal resistance 17.9 °C/W
ΨJT Junction-to-top characterization parameter 1 °C/W
ΨJB Junction-to-board characterization parameter 17.9 °C/W
RΘJC(bot) Junction-to-case (bottom) thermal resistance 7.8 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics - Power Consumption

Maximum and minimum values are specified over the operating free-air temperature range and nominal supply voltages. Typical values are specified at TA = 25°C, AVDD = IOVDD = 1.8 V, FIN = 5MHz, AIN = -1dBFS, Internal 1.2 V reference, 5 pF output load, and 50% clock duty cycle, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ADC3908D025
IAVDD Analog supply current Fs = 25MSPS, dual channel, DDR CMOS 28 31 mA
IIOVDD Digital supply current 3 9 mA
PDIS Power dissipation 56 mW
ADC3908S025
IAVDD Analog supply current Fs = 25MSPS, single channel, SDR CMOS 19 22 mA
IIOVDD Digital supply current 3 8 mA
PDIS Power dissipation 40 mW
ADC3908D065
IAVDD Analog supply current Fs = 65MSPS, dual channel, DDR CMOS 32 34 mA
IIOVDD Digital supply current 7 14 mA
PDIS Power dissipation 70 mW
ADC3908S065
IAVDD Analog supply current Fs = 65MSPS, single channel, SDR CMOS 21 24 mA
IIOVDD Digital supply current 6 13 mA
PDIS Power dissipation 49 mW
ADC3908D125
IAVDD Analog supply current Fs = 125MSPS, dual channel, DDR CMOS 38 40 mA
IIOVDD Digital supply current 12 21 mA
PDIS Power dissipation 90 mW
ADC3908S125
IAVDD Analog supply current Fs = 125MSPS, single channel, SDR CMOS 24 27 mA
IIOVDD Digital supply current 10 18 mA
PDIS Power dissipation 61 mW
Power down
PDIS Power consumption in power down 3 mW

6.6 Electrical Characteristics - DC Specifications

Maximum and minimum values are specified over the operating free-air temperature range and nominal supply voltages. Typical values are specified at TA = 25°C, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, Internal 1.2 V reference, and –1-dBFS differential input, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DC ACCURACY (25 MSPS)
No missing codes 8 bits
DNL Differential nonlinearity -0.35 ±0.15 +0.35 LSB
INL Integral nonlinearity -0.6 ±0.25 +0.6 LSB
VOS_ERR Offset error -2.75 ±1 +2.75 LSB
VOS_DRIFT Offset drift over temperature 0.001 LSB/ºC
GAINERR Gain error Internal Reference ±0.8 %FSR
GAINDRIFT Gain drift over temperature Internal Reference -102 ppm/ºC
DC ACCURACY (65 MSPS)
No missing codes 8 bits
DNL Differential nonlinearity -0.35 ±0.15 +0.35 LSB
INL Integral nonlinearity -0.6 ±0.25 +0.6 LSB
VOS_ERR Offset error -2.75 ±1 -2.75 LSB
VOS_DRIFT Offset drift over temperature 0.001 LSB/ºC
GAINERR Gain error Internal Reference ±0.8 %FSR
GAINDRIFT Gain drift over temperature Internal Reference -102 ppm/ºC
DC ACCURACY (125 MSPS)
No missing codes 8 bits
DNL Differential nonlinearity -0.35 ±0.15 +0.35 LSB
INL Integral nonlinearity -0.6 ±0.25 +0.6 LSB
VOS_ERR Offset error -2.75 ±1 2.75 LSB
VOS_DRIFT Offset drift over temperature 0.001 LSB/ºC
GAINERR Gain error Internal Reference ±0.8 %FSR
GAINDRIFT Gain drift over temperature Internal Reference -102 ppm/ºC
ADC ANALOG INPUT (INAP/M, INBP/M)
FS Input full scale Differential 1.9 Vpp
Single-ended 0.95 Vpp
CIN Differential input Capacitance FIN = 100 kHz 7 pF
VCM Input common mode voltage VOCM - 50mV 1.275 VOCM + 50mV V
VOCM Output common mode voltage 1.25 V
BW Analog Input Bandwidth (-3dB) 150 MHz
CLOCK INPUT
Input clock frequency ADC3908D125, ADC3908S125 5 125 MHz
ADC3908D065, ADC3908S065 5 65 MHz
ADC3908D025, ADC3908S025 5 25 MHz
VIH High level input voltage AVDD - 0.3 1.8 Vpp
VIL Low level input voltage 0 AVSS + 0.3 V
CIN Input capacitance 0.5 pF
Clock duty cycle 45 50 55 %
DIGITAL INPUTS (RESET, PDN, M0, M1, M2)
VIH High level input voltage 1.4 V
VIL Low level input voltage 0.4 V
IIH High level input current 90 150 uA
IIL Low level input current -150 -90 uA
CI Input capacitance 1.5 pF
DIGITAL CMOS OUTPUTS (D0:D07)
Output data rate per CMOS output pin 250 Mbps
VOH High level output voltage ILOAD = -400 uA IOVDD - 0.1 IOVDD V
VOL Low level output voltage ILOAD = 400 uA 0.1 V

6.7 Electrical Characteristics - AC Specifications (25 MSPS)

Maximum and minimum values are specified over the operating free-air temperature range and nominal supply voltages. Typical values are specified at TA = 25°C, AVDD = IOVDD = 1.8 V, FSCLK = 25 MSPS, FIN = 5MHz, AIN = -1dBFS, Internal 1.2 V reference , and 50% clock duty cycle, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
NSD Noise Spectral Density fIN = 10 MHz, AIN = -20 dBFS -120.8 dBFS/Hz
SNR Signal to noise ratio, excluding DC, HD2 to HD5 fIN = 1.1 MHz 49.9 dBFS
fIN = 5 MHz 48 49.9
fIN = 10 MHz 49.9
fIN = 20 MHz 49.9
SINAD Signal to noise and distortion ratio, excluding DC offset fIN = 1.1 MHz 49.6 dBFS
fIN = 5 MHz 49.7
fIN = 10 MHz 49.7
fIN = 20 MHz 49.7
ENOB Effective number of bits, excluding DC offset fIN = 1.1 MHz 8.0 Bit
fIN = 5 MHz 8.0
fIN = 10 MHz 8.0
fIN = 20 MHz 8.0
THD Total Harmonic Distortion (First five harmonics) fIN = 1.1 MHz -61 dBc
fIN = 5 MHz -63
fIN = 10 MHz -63
fIN = 20 MHz -64
SFDR Spur free dynamic range including second and third harmonic fIN = 1.1 MHz 63 dBFS
fIN = 5 MHz 60 65
fIN = 10 MHz 64
fIN = 20 MHz 64
SPUR Spur free dynamic range (excluding DC, HD2, HD3) fIN = 1.1 MHz 67 dBFS
fIN = 5 MHz 63 68
fIN = 10 MHz 68
fIN = 20 MHz 68
IMD3 Two tone inter-modulation distortion fIN = 8/10 MHz, AIN = -7 dBFS/tone -91 dBc
XTALK Channel-to-channel crosstalk Aggressor = 1.1 MHz 107 dBFS
Aggressor = 10 MHz 97
Aggressor = 20 MHz 93

6.8 Electrical Characteristics - AC Specifications (65 MSPS)

Maximum and minimum values are specified over the operating free-air temperature range and nominal supply voltages. Typical values are specified at TA = 25°C, AVDD = IOVDD = 1.8 V, FSCLK = 65 MSPS, FIN = 5MHz, AIN = -1dBFS, Internal 1.2 V reference , and 50% clock duty cycle, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
NSD Noise Spectral Density fIN = 10 MHz, AIN = -20 dBFS -125.0 dBFS/Hz
SNR Signal to noise ratio, excluding DC, HD2 to HD5 fIN = 1.1 MHz 49.8 dBFS
fIN = 5 MHz 47 49.8
fIN = 10 MHz 49.8
fIN = 20 MHz 49.8
fIN = 40 MHz 49.8
fIN = 70 MHz 49.8
SINAD Signal to noise and distortion ratio, excluding DC offset fIN = 1.1 MHz 49.6 dBFS
fIN = 5 MHz 49.7
fIN = 10 MHz 49.7
fIN = 20 MHz 49.7
fIN = 40 MHz 49.6
fIN = 70 MHz 49.6
ENOB Effective number of bits, excluding DC offset fIN = 1.1 MHz 8.0 Bit
fIN = 5 MHz 8.0
fIN = 10 MHz 8.0
fIN = 20 MHz 8.0
fIN = 40 MHz 8.0
fIN = 70 MHz 8.0
THD Total Harmonic Distortion (First five harmonics) fIN = 1.1 MHz -61 dBc
fIN = 5 MHz -63
fIN = 10 MHz -63
fIN = 20 MHz -64
fIN = 40 MHz -62
fIN = 70 MHz -61
SFDR Spur free dynamic range including second and third harmonic fIN = 1.1 MHz 62 dBFS
fIN = 5 MHz 60 64
fIN = 10 MHz 64
fIN = 20 MHz 65
fIN = 40 MHz 63
fIN = 70 MHz 62
SPUR Spur free dynamic range (excluding DC, HD2, HD3) fIN = 1.1 MHz 68 dBFS
fIN = 5 MHz 61 68
fIN = 10 MHz 68
fIN = 20 MHz 68
fIN = 40 MHz 68
fIN = 70 MHz 68
IMD3 Two tone inter-modulation distortion fIN = 8/10 MHz, AIN = -7 dBFS/tone -91 dBc
XTALK Channel-to-channel crosstalk Aggressor = 1.1 MHz 106 dBFS
Aggressor = 10 MHz 102
Aggressor = 20 MHz 97

 
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