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  • TPS23755 IEEE 802.3at PoE PD with No-Opto Flyback DC-DC Controller

    • SLVSDW2B December   2018  – November 2020 TPS23755

      PRODUCTION DATA  

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  • TPS23755 IEEE 802.3at PoE PD with No-Opto Flyback DC-DC Controller
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: DC-DC Controller Section
    6. 6.6 Electrical Characteristics: PoE and Control
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  CLS Classification
      2. 7.3.2  DEN Detection and Enable
      3. 7.3.3  Internal Pass MOSFET
      4. 7.3.4  DC-DC Controller Features
        1. 7.3.4.1 VCC, VB and Advanced PWM Startup
        2. 7.3.4.2 CS, Current Slope Compensation and Blanking
        3. 7.3.4.3 COMP, FB, CP and Opto-less Feedback
        4. 7.3.4.4 FRS Frequency Setting and Synchronization
        5. 7.3.4.5 Frequency Dithering for Spread Spectrum Applications
        6. 7.3.4.6 SST and Soft-Start of the Switcher
        7. 7.3.4.7 AUX_V, AUX_D and Secondary Adapter Or'ing
      5. 7.3.5  Internal Switching FET - DRAIN, RSNS, SRF and SRR
      6. 7.3.6  VPD Supply Voltage
      7. 7.3.7  VDD Supply Voltage
      8. 7.3.8  GND
      9. 7.3.9  VSS
      10. 7.3.10 Exposed Thermal PAD
    4. 7.4 Device Functional Modes
      1. 7.4.1 PoE Overview
      2. 7.4.2 Threshold Voltages
      3. 7.4.3 PoE Start-Up Sequence
      4. 7.4.4 Detection
      5. 7.4.5 Hardware Classification
      6. 7.4.6 Maintain Power Signature (MPS)
      7. 7.4.7 Start-Up and Converter Operation
      8. 7.4.8 PD Self-Protection
      9. 7.4.9 Adapter ORing
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Input Bridges and Schottky Diodes
        2. 8.2.2.2  Protection, D1
        3. 8.2.2.3  Capacitor, C1
        4. 8.2.2.4  Detection Resistor, RDEN
        5. 8.2.2.5  Classification Resistor, RCLS
        6. 8.2.2.6  Bulk Capacitance, CBULK
        7. 8.2.2.7  Output Voltage Feedback Divider, RAUX, R1,R2
        8. 8.2.2.8  Setting Frequency, RFRS
        9. 8.2.2.9  Frequency Dithering, RDTR and CDTR
        10. 8.2.2.10 Bias Voltage, CVB and DVB
        11. 8.2.2.11 Transformer design, T1
        12. 8.2.2.12 Current Sense Resistor, RCS
        13. 8.2.2.13 Current Slope Compensation, RS
        14. 8.2.2.14 Bias Supply Requirements, CCC, DCC
        15. 8.2.2.15 Switching Transformer Considerations, RVCC and CCC2
        16. 8.2.2.16 Primary FET Clamping, RCL, CCL, and DCL
        17. 8.2.2.17 Converter Output Capacitance, COUT
        18. 8.2.2.18 Secondary Output Diode Rectifier, DOUT
        19. 8.2.2.19 Slew rate control, RSRF and RSRR
        20. 8.2.2.20 Shutdown at Low Temperatures, DVDD and CVDD
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related documentation
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
  13. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • RJJ|23
Thermal pad, mechanical data (Package|Pins)
Orderable Information
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  • slvsdw2b_pm
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DATA SHEET

TPS23755 IEEE 802.3at PoE PD with No-Opto Flyback DC-DC Controller

1 Features

  • Complete IEEE 802.3at PD solution for type 1 PoE
    • Ethernet Alliance (EA) logo certified designs available
    • Robust 100-V, 0.36-Ω (typ) hotswap MOSFET
    • Programmable classification level
  • Integrated PWM controller with 0.77-Ω (typ) 150-V power MOSFET
    • Flyback controller with PSR
      • Supports CCM operation with secondary side diode rectifier
      • ±3% (typ, 12-V Output) Load regulation (5%-100% range)
    • Supports low-side switch buck topology
    • Adjustable switching frequency with synchronization
    • advanced startup
    • Programmable slew rate and frequency dithering for enhanced EMI reduction
  • Secondary side adapter priority control with smooth transition
  • –40°C to 125°C Junction temperature range
  • Small 6-mm x 4-mm VSON package

2 Applications

  • IEEE 802.3at compliant powered devices
  • Security cameras
  • IP phones
  • Access points

3 Description

The TPS23755 device combines a Power over Ethernet (PoE) powered device (PD) interface, a 150-V switching power FET, and a current-mode DC-DC controller optimized for flyback topology. The high level of integration along with primary side regulation (PSR), spread spectrum frequency dithering (SSFD), and advanced startup makes the TPS23755 an ideal solution for size-constrained applications. The PoE implementation supports the IEEE 802.3at standard as a 13-W, Type 1 PD.

The PSR feature of the DC-DC controller uses feedback from an auxiliary winding for control of the output voltage, eliminating the need for external shunt regulator and optocoupler. It is optimized for operation with secondary side diode rectifier (typically 12-V output or higher). Typically, the converter operates in continuous conduction mode (CCM) at a switching frequency of 250 kHz.

SFFD and slew rate control helps to minimize the size and cost of the EMI filter. Advanced Startup allows the use of minimal bias capacitor while simplifying converter startup and hiccup design.

Secondary auxiliary power detect capability provides priority for a secondary side power adapter, while ensuring smooth transition to and from PoE input power, with no efficiency or thermal trade-off.

The DC-DC controller features internal soft-start, slope compensation, and blanking. For non-isolated applications, the buck topology is also supported by the TPS23755.

Device Information(1)
PART NUMBERPACKAGEBODY SIZE (NOM)
TPS23755VSON (24)6.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
GUID-D530FD99-020C-4CBB-9C3C-2E8550253B54-low.gifSimplified Application
GUID-7790716A-20B0-4ED2-9A6D-9D5BEBC5B7B8-low.gifEfficiency Vs. Load Current, 12 V Output

4 Revision History

Changes from Revision A (January 2019) to Revision B (November 2020)

  • Updated the numbering format for tables, figures and cross-references throughout the documentGo
  • Updated Figure 3-1 with DvbGo
  • Added, "...and 6.2-V Zener diode..."Go
  • Added paragraph, "VB is the 5-V bias rail..."Go
  • Updated Figure 8-1 and Figure 8-2 to include DvbGo
  • Added section, "Bias Voltage, CVB and DVB"Go

Changes from Revision * (December 2018) to Revision A (January 2019)

  • Changed device status to Production Data Go

5 Pin Configuration and Functions

GUID-0CFA669D-A8CC-4C99-9034-11A127EA64FE-low.gif Figure 5-1 RJJ Package24-Pin VSONTop View
Table 5-1 Pin Functions
PINI/ODESCRIPTION
NO.NAME
1RSNSOSwitching Power FET source connection. Connect to the external power current sense resistor.
2CPOCP provides the clamp for the primary side regulation loop. Connect this pin to the lower end of the second primary side winding of the transformer.
3GND—Power ground used by the flyback power FET gate driver and CP. Connect to RTN.
4SRRISwitching FET Gate sinking current input, used for EMI control. Connect a resistance from SRR to GND to control the Vds rate of rise.
5SRFISwitching FET Gate sourcing current input, used for EMI control. Connect a resistance from SRF to VB to control the Vds rate of fall.
6VBO5-V bias rail for the switching FET gate driver circuit. For internal use only. Bypass with a 0.1-μF ceramic capacitor and 6.2-V Zener diode to GND pin.
7AUX_DIAuxiliary supply detect, internally pulled-up to approximately 5 V. Pull this pin low, typically through an optocoupler from the secondary side, to step down the output voltage of the DC-DC converter when a secondary side auxiliary supply is connected.
8CSIDC-DC controller current sense input. Connect directly to the external power current sense resistor.
9DTHROUsed for spread spectrum frequency dithering. Connect a capacitor from DTHR to RTN and a resistor from DTHR to FRS. If dithering is not used, short DTHR to VB pin.
10FRSI/OThis pin controls the switching frequency of the DC-DC converter. Tie a resistor from this pin to RTN to set the frequency.
11RTN—RTN is the output of the PoE hotswap and the reference ground for the DC-DC controller.
12VSS—Negative power rail derived from the PoE source.
13VDD—Source of DC-DC converter start-up current. Connect to VPD for most applications.
14VPD—Positive input power rail for PoE interface circuit. Derived from the PoE source. Bypass with a 0.1 µF to VSS and protect with a TVS.
15DENI/OConnect a 24.9-kΩ resistor from DEN to VPD to provide the PoE detection signature. Pulling this pin to VSS during powered operation causes the internal hotswap MOSFET to turn off.
16CLSOConnect a resistor from CLS to VSS to program the classification current.
17NC—No connect pin. Leave open.
18FBIConverter error amplifier inverting (feedback) input. It is typically driven by a voltage divider from the auxiliary winding. Also connect to the COMP compensation network.
19COMPOCompensation output of the DC-DC convertor error amplifier. Connect the compensation networks from this pin to the FB pin to compensate the converter.
20AUX_VOAUX_V works with AUX_D to step down the output voltage setting of the DC-DC converter when an auxiliary supply is detected. Typically connected to FB pin through a resistor which defines the new voltage setting.
21VCCI/ODC/DC converter bias voltage. The internal startup current source and converter bias winding output power this pin. Connect a 1-µF minimum ceramic capacitor to RTN.
23NC—No connect pin. Leave open.
24DRAINODrain connection to the internal switching power MOSFET of the DC/DC controller.
-PAD—The exposed thermal pad must be connected to VSS. A large fill area is required to assist in heat dissipation.
A1-A4ANCHORS—Should be soldered to PCB for mechanical performance. These pins are not connected internally.

6 Specifications

6.1 Absolute Maximum Ratings

Voltage are with respect to VVSS (unless otherwise noted)(1)
MINMAXUNIT
Input voltageVDD, VPD, DEN, GND, RTN(2)–0.3100V
VDD to RTN–0.3100
AUX_D, FB, CS, all to RTN–0.36.5
SRF to GND–0.36.5
VoltageCLS(3)–0.36.5V
FRS(3), COMP(3), VB(3), SRR(3), DTHR(3), RSNS(3), AUX_V(3), all to RTN–0.36.5
VCC to RTN–0.319
DRAIN to GND–0.3150
CP to GND–0.360
GND to RTN–0.30.3
Sourcing currentVB, VCCInternally limitedmA
CLS35
COMPInternally limited
Sinking currentRTNInternally limitedmA
DEN1
AUX_V5
COMPInternally limited
IDRAINSwitching DRAIN peak current limit2A
Switching DRAIN peak current limit, Buck topology with 16% duty-cycle3
Peak sourcing currentCP1.5A
TJ(max)Maximum junction temperatureInternally Limited°C
TstgStorage temperature–65150°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) IRTN = 0 for VRTN > 80 V.
(3) Do not apply voltage to these pins.

6.2 ESD Ratings

VALUEUNIT
V(ESD)Electrostatic dischargeHuman-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)±2000V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)±500
IEC 61000-4-2 contact discharge(3)±8000
IEC 61000-4-2 air-gap discharge(3)±15000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(3) ESD per EN61000-4-2, applied between RJ-45 and output ground of the TPS23755EVM-894 evaluation module. These were the test levels, not the failure threshold.

 
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