TPS37-Q1 Wide VIN 65 V Dual Channel Overvoltage & Undervoltage (OV & UV) Detector with Programmable Sense and Reset Delay Function for Automotive
- SNVSBD9E august 2020 – august 2023 TPS37-Q1
  
  PRODUCTION DATA

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Data Sheet

TPS37-Q1 Wide V_IN 65 V Dual Channel Overvoltage & Undervoltage (OV & UV) Detector with Programmable Sense and Reset Delay Function for Automotive

1 Features

AEC-Q100 qualified with the following results:
- Device temperature grade 1: –40°C to +125°C ambient operating temperature T_A
- Device HBM ESD classification level 2
- Device CDM ESD classification level C7B
Functional Safety - Capable
- Documentation available to functional safety system design
Wide supply voltage range: 2.7 V to 65 V
SENSE and RESET pins are 65 V graded
Low quiescent current: 1 µA (typical)
Flexible and wide voltage threshold options
Table 11-1
- 2.7 V to 36 V (1.5% maximum accuracy)
- 800 mV option (1% maximum accuracy)
Built-in hysteresis (V_HYS)
- Percentage options: 2% to 13% (1% steps)
- Fixed options: V_TH < 8 V = 0.5 V, 1 V, 1.5 V,
  2 V, 2.5 V
Programmable reset time delay
- 10 nF = 12.8 ms, 10 μF = 12.8 s
Programmable sense time delay
- 10 nF = 1.28 ms, 10 μF = 1.28 s
Manual Reset (MR) feature
Output topology: Open-Drain or Push-Pull

2 Applications

3 Description

The TPS37-Q1 is a 65 V input voltage detector with
1 μA I_DD, 1% accuracy, and with a fast 10 μs detection time. This device can be connected directly to
12 V / 24 V automotive battery system for continuous monitoring of over (OV) and under (UV) voltage conditions; with its internal resistor divider, it offers the smallest total solution size. Wide hysteresis voltage options are available to ignore cold crank, start-stop and various car battery voltage transients. Built-in hysteresis on the SENSE pins prevents false reset signals when monitoring a supply voltage rail.

The separate VDD and SENSE pins allow redundancy sought by high-reliability automotive systems and SENSE can monitor higher and lower voltages than VDD. Optional use of external resistors are supported by the high impedance input of the SENSE pins. CTSx and CTRx pins allow delay adjustability on the rising and falling edges of the RESET signals. Also, CTSx functions as a debouncer by ignoring voltage glitches on the monitored voltage rails; CTRx operates as a manual reset (MR) that can be used to force a system reset.

TPS37-Q1 is available in WSON or SOT-23 package. The WSON package has wettable flanks allowing the facilitation for Automatic Optical Inspection (AOI) and low resolution X-ray inspection. The central pad is non-conductive to increase the creepage between VDD and GND per guidelines in IEC60664.

Device Information

PART NUMBER	PACKAGE ⁽¹⁾	BODY SIZE (NOM)
TPS37-Q1	WSON (10) (DSK)	2.5 mm × 2.5 mm
TPS37-Q1	SOT-23 (14) (DYY)	4.1 mm × 1.9 mm

(1) For package details, see the mechanical drawing addendum at the end of the data sheet.

Typical Application Circuit

Typical I_DD vs V_DD

4 Revision History

Changes from Revision D (July 2023) to Revision E (August 2023)

Add Funtional safety statement and removed latch functionalityGo
Add Vhyst and accurary diagramGo
Added CTS and CTR value plotsGo
Fixed output topologyGo
Corrected CTR to CTS on EQGo

Changes from Revision C (December 2021) to Revision D (July 2023)

Removed Product Preivew for the DYY package throughoutGo

Changes from Revision B (September 2021) to Revision C (December 2021)

Advance Information to Production Data releaseGo

5 Device Comparison

Contact TI sales representatives or consult TI's E2E forum for details and availability; minimum order quantities may apply.

Sense logic: OV = overvoltage; UV = undervoltage
Reset topology: PP = Push-Pull; OD = Open-Drain
Reset logic: L = Active-Low; H = Active-High
A to I hysteresis options are only available for 2.7 V to 8 V threshold options

6 Pin Configuration and Functions

Figure 6-1 DSK Package,
10-Pin WSON,
TPS37-Q1 (Top View)

Figure 6-2 DYY Package,
14-Pin SOT-23,
TPS37-Q1 (Top View)

Table 6-1 Pin Functions

PIN NAME	WSON (DSK)	SOT23 (DYY)	I/O	DESCRIPTION
PIN NAME	PIN NUM.	PIN NUM.	I/O	DESCRIPTION
VDD	1	1	I	Input Supply Voltage: Bypass with a 0.1 µF capacitor to GND.
SENSE1	2	3	I	This pin is connected to the voltage that will be monitored for fixed variants or to a resistor divider for the adjustable variant. When the voltage on SENSE1 pin transitions above the upper threshold voltage of V_IT+, RESET1/RESET1 asserts after the sense time delay, set by CTS1. When the voltage on the SENSE1 pin transitions below the upper threshold voltage of V_IT+ - V_HYS, RESET1/RESET1 deasserts after the reset time delay, set by CTR1. For noisy applications, placing a 10 nF to 100 nF ceramic capacitor close to this pin may be needed for optimum performance.
SENSE2	3	4	I	This pin is connected to the voltage that will be monitored for fixed variants or to a resistor divider for the adjustable variant. When the voltage on SENSE2 pin transitions below the lower threshold voltage of V_IT-, RESET2/RESET2 asserts after the sense time delay, set by CTS2. When the voltage on the SENSE2 pin transitions above the lower threshold voltage of V_IT- + V_HYS, RESET2/RESET2 deasserts after the reset time delay, set by CTR2. For noisy applications, placing a 10 nF to 100 nF ceramic capacitor close to this pin may be needed for optimum performance.
RESET1/RESET1	4	6	O	Output Reset Signal For Channel 1: See Section 5 for output topology options. RESET1/RESET1 asserts when SENSE1 rises outside of the upper voltage threshold. RESET1/RESET1 remains asserted for the reset time delay period after SENSE1 transitions out of an overvoltage (OV) fault condition. For active low open-drain reset output, an external pullup resistor is required. Do not place external pullup resistors on push-pull outputs. Reset output signal for: SENSE1 Sensing Topology: Overvoltage (OV) Output topology: Open Drain or Push Pull, Active Low or Active High
RESET2/RESET2	5	7	O	Output Reset Signal For Channel 2: See Section 5 for output topology options. RESET2/RESET2 asserts when SENSE2 falls outside of the lower voltage threshold. RESET2/RESET2 remains asserted for the reset time delay period after SENSE2 transitions out of an undervoltage (UV) fault condition. For active low open-drain reset output, an external pullup resistor is required. Reset output signal for: SENSE2 Sensing Topology: Undervoltage (UV) Output topology: Open Drain, Active Low or Active High
CTR1/ MR	6	9	-	Channel 1 RESET Time Delay: User-programmable reset time delay for RESET1/RESET1. Connect an external capacitor for adjustable time delay or leave the pin floating for the shortest delay. Manual Reset: If this pin is driven low, the RESET1/RESET1 output will reset and become asserted. The pin can be left floating or be connected to a capacitor. This pin should not be driven high.
CTR2/ MR	9	12	-	Channel 2 RESET Time Delay: User-programmable reset time delay for RESET2/RESET2. Connect an external capacitor for adjustable time delay or leave the pin floating for the shortest delay. Manual Reset: If this pin is driven low, the RESET2/RESET2 output will reset and become asserted. The pin can be left floating or be connected to a capacitor. This pin should not be driven high.
GND	10	8, 13	-	Ground. All GND pins must be electrically connected to the board ground.
NC	PAD	2, 5, 14	-	The PAD for the DSK package is not internally connected, the PAD can be connected to GND or be left floating. For the DYY package, NC stands for “No Connect”. The pins are to be left floating.
CTS1	7	10	O	Channel 1 SENSE Time Delay: Capacitor programmable sense delay: CTS1 pin offers a user-adjustable sense delay time when asserting a reset condition. Connecting this pin to a ground-referenced capacitor sets the RESET1/RESET1 delay time to assert.
CTS2	8	11	O	Channel 2 SENSE Time Delay: Capacitor programmable sense delay: CTS2 pin offers a user-adjustable sense delay time when asserting a reset condition. Connecting this pin to a ground-referenced capacitor sets the RESET2/RESET2 delay time to assert.