SLVSDF5D
September 2017 – October 2019
TPS50601A-SP
PRODUCTION DATA.
1
Features
Efficiency at VIN = PVIN = 5 V
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
VIN and Power VIN Pins (VIN and PVIN)
7.3.2
Voltage Reference
7.3.3
Adjusting the Output Voltage
7.3.4
Safe Start-Up Into Prebiased Outputs
7.3.5
Error Amplifier
7.3.6
Slope Compensation
7.3.7
Enable and Adjust UVLO
7.3.8
Adjustable Switching Frequency and Synchronization (SYNC)
7.3.9
Slow Start (SS/TR)
7.3.10
Power Good (PWRGD)
7.3.11
Sequencing (SS/TR)
7.3.12
Output Overvoltage Protection (OVP)
7.3.13
Overcurrent Protection
7.3.13.1
High-Side MOSFET Overcurrent Protection
7.3.13.2
Low-Side MOSFET Overcurrent Protection
7.3.14
Thermal Shutdown
7.3.15
Turn-On Behavior
7.3.16
Small Signal Model for Frequency Compensation
7.4
Device Functional Modes
7.4.1
Fixed-Frequency PWM Control
7.4.2
Continuous Current Mode (CCM) Operation
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
Operating Frequency
8.2.2.2
Output Inductor Selection
8.2.2.3
Output Capacitor Selection
8.2.2.4
Slow Start Capacitor Selection
8.2.2.5
Undervoltage Lockout (UVLO) Set Point
8.2.2.6
Output Voltage Feedback Resistor Selection
8.2.2.7
Compensation Component Selection
8.2.3
Parallel Operation
8.2.4
Application Curve
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
Device and Documentation Support
11.1
Documentation Support
11.1.1
Related Documentation
11.2
Receiving Notification of Documentation Updates
11.3
Community Resources
11.4
Trademarks
11.5
Electrostatic Discharge Caution
11.6
Glossary
12
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
HKH|20
MCDF004D
KGD|0
Thermal pad, mechanical data (Package|Pins)
Orderable Information
slvsdf5d_oa
slvsdf5d_pm
1
Features
5962-10221:
Radiation hardened up to TID 100 krad(Si)
ELDRS free 100 krad(Si) – 10 mrad(Si)/s
Single lhup (SEL) Immune to
LET = 75 MeV-cm
2
/mg
SEB and SEGR immune to 75 MeV-cm
2
/mg, SOA Curve Available
SET/SEFI Cross-section plot available
peak efficiency: 96.6% (V
O
= 3.3 V)
Integrated 58-mΩ/50-mΩ MOSFETs
Power rail: 3 to 7 V on VIN
6-A Maximum output current
Flexible switching frequency options:
100-kHz to 1-MHz Adjustable internal oscillator
External sync capability: 100 kHz to 1 MHz
Sync pin can be configured as a 500-kHz output for master/slave applications
0.804-V ±1.5% Voltage reference overtemperature, radiation, and line and load regulation
Monotonic start-up into prebiased outputs
Adjustable soft start through external capacitor
Input enable and power-good output for power sequencing
Power good output monitor for undervoltage and overvoltage
Adjustable input undervoltage lockout (UVLO)
20-Pin Ultra-small, thermally-enhanced ceramic flatpack package (hkh) for space applications
Efficiency at VIN = PVIN = 5 V