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CC115L Value Line Transmitter
SWRS105B
May 2011 – June 2014
CC115L
PRODUCTION DATA.
CONTENTS
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CC115L Value Line Transmitter
1
Device Overview
1.1
Features
1.2
Applications
1.3
Description
1.4
Functional Block Diagram
2
Revision History
3
Terminal Configuration and Functions
3.1
Pin Diagram
3.2
Signal Descriptions
4
Specifications
4.1
Absolute Maximum Ratings
4.2
Handling Ratings
4.3
Recommended Operating Conditions
4.4
General Characteristics
4.5
Current Consumption
4.5.1
Typical TX Current Consumption over Temperature and Supply Voltage, 868 MHz
4.5.2
Typical TX Current Consumption over Temperature and Supply Voltage, 915 MHz
4.6
RF Transmit Section
4.6.1
Typical Variation in Output Power over Temperature and Supply Voltage, 868 MHz
4.6.2
Typical Variation in Output Power over Temperature and Supply Voltage, 915 MHz
4.7
Crystal Oscillator
4.8
Frequency Synthesizer Characteristics
4.9
DC Characteristics
4.10
Power-On Reset
4.11
Thermal Characteristics
5
Detailed Description
5.1
Overview
5.2
Functional Block Diagram
5.3
Configuration Overview
5.4
Configuration Software
5.5
4-wire Serial Configuration and Data Interface
5.5.1
Chip Status Byte
5.5.2
Register Access
5.5.3
SPI Read
5.5.4
Command Strobes
5.5.5
TX FIFO Access
5.5.6
PATABLE Access
5.6
Microcontroller Interface and Pin Configuration
5.6.1
Configuration Interface
5.6.2
General Control and Status Pins
5.7
Data Rate Programming
5.8
Packet Handling Hardware Support
5.8.1
Packet Format
5.8.1.1
Packet Length > 255
5.8.2
Packet Handling
5.8.3
Packet Handling in Firmware
5.9
Modulation Formats
5.9.1
Frequency Shift Keying
5.9.2
Amplitude Modulation
5.10
Radio Control
5.10.1
Power-On Start-Up Sequence
5.10.1.1
Automatic POR
5.10.1.2
Manual Reset
5.10.2
Crystal Control
5.10.3
Voltage Regulator Control
5.10.4
Transmit Mode (TX)
5.10.5
Timing
5.10.5.1
Overall State Transition Times
5.10.5.2
Frequency Synthesizer Calibration Time
5.11
TX FIFO
5.12
Frequency Programming
5.13
VCO
5.13.1
VCO and PLL Self-Calibration
5.14
Voltage Regulators
5.15
Output Power Programming
5.16
General Purpose and Test Output Control Pins
5.17
Asynchronous and Synchronous Serial Operation
5.17.1
Asynchronous Serial Operation
5.17.2
Synchronous Serial Operation
5.18
System Considerations and Guidelines
5.18.1
SRD Regulations
5.18.2
Calibration in Multi-Channel Systems
5.18.3
Wideband Modulation when not Using Spread Spectrum
5.18.4
Data Burst Transmissions
5.18.5
Continuous Transmissions
5.18.6
Increasing Output Power
5.19
Configuration Registers
5.19.1
Configuration Register Details - Registers with preserved values in SLEEP state
5.19.2
Configuration Register Details - Registers that Lose Programming in SLEEP State
5.19.3
Status Register Details
5.20
Development Kit Ordering Information
6
Applications, Implementation, and Layout
6.1
Bias Resistor
6.2
Balun and RF Matching
6.3
Crystal
6.4
Reference Signal
6.5
Additional Filtering
6.6
Power Supply Decoupling
6.7
PCB Layout Recommendations
7
Device and Documentation Support
7.1
Device Support
7.1.1
Device Nomenclature
7.2
Documentation Support
7.2.1
Related Documentation from Texas Instruments
7.2.2
Community Resources
7.3
Trademarks
7.4
Electrostatic Discharge Caution
7.5
Export Control Notice
7.6
Glossary
7.7
Additional Acronyms
8
Mechanical Packaging and Orderable Information
8.1
Packaging Information
IMPORTANT NOTICE
Package Options
Mechanical Data (Package|Pins)
RGP|20
MPQF126G
Thermal pad, mechanical data (Package|Pins)
RGP|20
QFND856
Orderable Information
swrs105b_oa
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