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ADS890xB 20 位具有集成式基准缓冲器和增强性能特性的高速 SAR ADC 特性
ZHCSFO6A
November 2016 – June 2017
ADS8900B
,
ADS8902B
,
ADS8904B
PRODUCTION DATA.
CONTENTS
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ADS890xB 20 位具有集成式基准缓冲器和增强性能特性的高速 SAR ADC 特性
1
特性
2
应用
3
说明
4
修订历史记录
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements
6.7
Switching Characteristics
6.8
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
LDO Module
7.3.2
Reference Buffer Module
7.3.3
Converter Module
7.3.3.1
Sample-and-Hold Circuit
7.3.3.2
Internal Oscillator
7.3.3.3
ADC Transfer Function
7.3.4
Interface Module
7.4
Device Functional Modes
7.4.1
RST State
7.4.2
ACQ State
7.4.3
CNV State
7.5
Programming
7.5.1
Output Data Word
7.5.2
Data Transfer Frame
7.5.3
Interleaving Conversion Cycles and Data Transfer Frames
7.5.4
Data Transfer Protocols
7.5.4.1
Protocols for Configuring the Device
7.5.4.2
Protocols for Reading From the Device
7.5.4.2.1
Legacy, SPI-Compatible (SYS-xy-S) Protocols
7.5.4.2.2
SPI-Compatible Protocols with Bus Width Options
7.5.4.2.3
Source-Synchronous (SRC) Protocols
7.5.4.2.3.1
Output Clock Source Options with SRC Protocols
7.5.4.2.3.2
Bus Width Options With SRC Protocols
7.5.4.2.3.3
Output Data Rate Options With SRC Protocols
7.5.5
Device Setup
7.5.5.1
Single Device: All multiSPI Options
7.5.5.2
Single Device: Minimum Pins for a Standard SPI Interface
7.5.5.3
Multiple Devices: Daisy-Chain Topology
7.5.5.4
Multiple Devices: Star Topology
7.6
Register Maps
7.6.1
Device Configuration and Register Maps
7.6.1.1
PD_CNTL Register (address = 04h) [reset = 00h]
7.6.1.2
SDI_CNTL Register (address = 008h) [reset = 00h]
7.6.1.3
SDO_CNTL Register (address = 0Ch) [reset = 00h]
7.6.1.4
DATA_CNTL Register (address = 010h) [reset = 00h]
7.6.1.5
PATN_LSB Register (address = 014h) [reset = 00h]
7.6.1.6
PATN_MID Register (address = 015h) [reset = 00h]
7.6.1.7
PATN_MSB Register (address = 016h) [reset = 00h]
7.6.1.8
OFST_CAL Register (address = 020h) [reset = 00h]
7.6.1.9
REF_MRG Register (address = 030h) [reset = 00h]
8
Application and Implementation
8.1
Application Information
8.1.1
ADC Reference Driver
8.1.2
ADC Input Driver
8.1.2.1
Charge-Kickback Filter
8.1.2.2
Input Amplifier Selection
8.2
Typical Application
8.2.1
Data Acquisition (DAQ) Circuit for Lowest Distortion and Noise Performance With Differential Input
8.2.1.1
Design Requirements
8.2.1.2
Detailed Design Procedure
8.2.1.3
Application Curves
8.2.2
DAQ Circuit With FDA Input Driver and Single-Ended or Differential Input
8.2.3
Design Requirements
8.2.4
Detailed Design Procedure
8.2.5
Application Curves
9
Power-Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.1.1
Signal Path
10.1.2
Grounding and PCB Stack-Up
10.1.3
Decoupling of Power Supplies
10.1.4
Reference Decoupling
10.1.5
Differential Input Decoupling
10.2
Layout Example
11
器件和文档支持
11.1
文档支持
11.1.1
相关文档
11.2
相关链接
11.3
接收文档更新通知
11.4
社区资源
11.5
商标
11.6
静电放电警告
11.7
Glossary
12
机械、封装和可订购信息
重要声明
封装选项
机械数据 (封装 | 引脚)
RGE|24
MPQF124G
散热焊盘机械数据 (封装 | 引脚)
RGE|24
QFND136Y
订购信息
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zhcsfo6a_pm
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