TDC7200 适用于激光雷达飞行时间、磁致伸缩和流量计应用的时间数字转换器
- ZHCSDF0C February 2015 – August 2015 TDC7200
  
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TDC7200 适用于激光雷达飞行时间、磁致伸缩和流量计应用的时间数字转换器

本资源的原文使用英文撰写。为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

分辨率：55ps
标准偏差：35ps
测量范围:
- 模式 1：12ns 至 500ns
- 模式 2：250ns 至 8ms
低功耗：0.5μA (2SPS)
最多支持 5 个 STOP 信号
自主多周期平均模式，可实现低功耗
电源电压：2V 至 3.6V
工作温度范围：-40°C 至 85°C
用于配置和寄存器访问的 SPI 主器件接口

2 应用

流量计：水表、燃气表和热量计
磁致伸缩位置/液位感测
无人机（激光雷达和声纳）的飞行时间、计量设备和投影仪
热量分配表

3 说明

TDC7200 是一款时间 - 数字转换器 (TDC)，适用于水表、燃气表和热量计等超声波感测装置。与 TDC1000（超声波模拟前端）配套使用时，TDC7200 可与 MSP430、电源、无线器件以及相关源代码一起构成一套完整的德州仪器 (TI) 超声波感测解决方案。

时间数字转换器 (TDC) 可执行秒表功能，测量 START 脉冲与多达 5 个 STOP 脉冲之间的时间间隔（渡越时间，即 TOF）。这一功能使得用户能够灵活选择回声性能最佳的 STOP 脉冲。

该器件内置自校准时基，可对时间和温度偏差进行补偿。这一自校准功能使得时间数字转换器能够获得皮秒级精度。因此，TDC7200 非常适用于注重高精度零流量和低流量测量的流量计应用。

TDC7200 置于自主多周期平均模式下时，可降低系统功耗，非常适合电池供电式流量计。在此模式下，主器件会进入休眠模式以实现节能，并会在测量序列完成后由 TDC 中断唤醒。

器件信息⁽¹⁾

部件号	封装	封装尺寸（标称值）
TDC7200	TSSOP (14)	5.00mm x 4.40mm

要了解所有可用封装，请见数据表末尾的可订购产品附录。

4 修订历史记录

Changes from B Revision (June 2015) to C Revision

已将数据表标题由 TDC7200 适用于水和燃气流量感测、磁致伸缩位置感测以及激光雷达计量应用的时间 - 数字转换器更改为 TDC7200 适用于激光雷达飞行时间、磁致伸缩和流量计应用的时间 - 数字转换器 Go

Changes from A Revision (March 2015) to B Revision

已将数据表标题由 TDC7200 适用于水、燃气、热量计量应用的时间 - 数字转换器更改为 TDC7200 适用于水和燃气流量感测、磁致伸缩位置感测和激光雷达计量应用的时间 - 数字转换器Go
已更改应用列表，新增了“磁致伸缩位置感测”和“激光雷达计量”Go

Changes from * Revision (February 2015) to A Revision

Changed “单页产品预览”至“完整数据表”Go
Changed ESD Ratings tableGo

5 Companion Device

PART NO.	TITLE
TDC1000	Ultrasonic Sensing Analog Front End for Level, Concentration, Flow and Proximity Sensing

6 Pin Configuration and Functions

PW Package

14-Pin TSSOP

Top View

Pin Functions

PIN		I/O	DESCRIPTION
NAME	NO.	I/O	DESCRIPTION
ENABLE	1	Input	Enable signal to TDC
TRIGG	2	Output	Trigger output signal
START	3	Input	START signal to TDC
STOP	4	Input	STOP signal to TDC
CLOCK	5	Input	Clock Input to TDC
N.C.	6	–	Not Connected
GND	7	Ground	Ground
INTB	8	Output	Interrupt to MCU, active low (open drain)
DOUT	9	Output	SPI Data Output
DIN	10	Input	SPI Data Input
CSB	11	Input	SPI Chip Select, active low
SCLK	12	Input	SPI clock
VREG	13	Output	LDO Output terminal for external decoupling cap
VDD	14	Power	Supply input

7 Specifications

7.1 Absolute Maximum Ratings

T_A = 25°C , VDD = 3.3V, GND = 0V (unless otherwise noted).⁽¹⁾⁽²⁾⁽³⁾

		MIN	MAX	UNIT
V_DD	Supply voltage	–0.3	3.9	V
V_I	Terminal input voltage	–0.3	V_DD+0.3	V
V_{DIFF_IN}	\|Voltage differential\| between any two input terminals		3.9	V
V_{IN_GND_VDD}	\|Voltage differential\| between any input terminal and GND or VDD		3.9	V
I_I	Input current at any pin	–5	5	mA
T_A	Ambient temperature	-40	125	°C
T_stg	Storage temperature	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum

(3) All voltages are with respect to ground, unless otherwise specified.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±1000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±250	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

T_A = 25°C , VDD = 3.3V, GND = 0V (unless otherwise noted).

		MIN	NOM	MAX	UNIT
V_DD	Supply voltage	2		3.6	V
V_I	Terminal voltage	0		VDD	V
V_IH	Voltage input high	0.7 × VDD		3.6	V
V_IL	Voltage input low	0		0.3 × VDD	V
F_{CALIB_CLK}	Frequency (Reference/Calibration Clock)	1 ⁽¹⁾	8	16	MHz
DUTY_CLOCK	Input clock duty cycle		50%
TIMING REQUIREMENTS: Measurement Mode 1 ⁽¹⁾
T1_{STARTSTOP_Min}	Minimum Time between Start and Stop Signal	12			ns
T1_{STOPSTOP_Min}	Minimum Time between 2 Stop Signals	67			ns
T1_{STARTSTOP_Max}	Maximum time bet. Start and Stop Signal			500	ns
T1_{STOPSTOP_Max}	Maximum time bet. Start and last Stop Signal			500	ns
TIMING REQUIREMENTS: Measurement 2 ⁽¹⁾
T2_{STARTSTOP_Min}	Minimum Time between Start and Stop Signal	2×t_CLOCK			s
T2_{STOPSTOP_Min}	Minimum Time between 2 Stop Signals	2×t_CLOCK			s
T2_{STARTSTOP_Max}	Maximum time bet. Start and Stop Signal			(2¹⁶-2)×t_CLOCK	s
T2_{STOPSTOP_Max}	Maximum. time bet. Start and last Stop Signal			(2¹⁶-2)×t_CLOCK	s
TIMING REQUIREMENTS: ENABLE INPUT
T_REN	Rise Time for Enable Signal (20%-80%)		1 to 100		ns
T_FEN	Fall Time for Enable Signal (20%-80%)		1 to 100		ns
TIMING REQUIREMENTS: START, STOP, CLOCK
T_RST, T_FST	Maximum rise, fall time for START, STOP signals (20%-80%)		1		ns
T_RXCLK, T_FXCLK	Maximum rise, fall time for external CLOCK (20%-80%)		1		ns
TIMING REQUIREMENTS: TRIGG
T_TRIGSTART	Time from TRIG to START		5		ns
TEMPERATURE
T_A	Ambient temperature	–40		85	°C
T_J	Junction temperature	–40		85	°C

7.4 Thermal Information

THERMAL METRIC⁽²⁾		TDC7200	UNIT
		PW [TSSOP]
		14 PINS
R_θJA	Junction-to-ambient thermal resistance	134.9	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	63
R_θJB	Junction-to-board thermal resistance	76.8
ψ_JT	Junction-to-top characterization parameter	12.4
ψ_JB	Junction-to-board characterization parameter	76.2
θ_JA	Package thermal impedance	113

(1) Specified by design.

(2) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

T_A = 25°C , VDD = 3.3 V, GND = 0 V (unless otherwise noted).

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
TDC CHARACTERISTICS
LSB	Resolution	Single shot measurement		55		ps
T_ACC-2	Accuracy (Mode 2) ⁽¹⁾	CLOCK = 8 MHz		28		ps
T_STD-2	Standard Deviation (Mode 2)	Measured time = 100 µs		50		ps
T_STD-2	Standard Deviation (Mode 2)	Measured time = 1 µs		35		ps
OUTPUT CHARACTERISTICS: TRIGG, INTB, DOUT
V_OH	Output voltage high	Isource = -2 mA	2.31	2.95		V
V_OL	Output voltage low	Isink = 2 mA		0.35	0.99	V
INPUT CHARACTERISTICS: ENABLE, START, STOP, CLOCK, DIN, CSB,SCLK
C_in	Input capacitance ⁽²⁾			3		pF
POWER CONSUMPTION (see Measurement Mode 1 and Measurement Mode 2)
I_sh	Shutdown current	EN = LOW		0.3	2	µA
I_QA	Quiescent Current A	EN = HIGH; TDC running		1.35		mA
I_QB	Quiescent Current B	EN = HIGH; TDC OFF, Clock Counter running		71		µA
I_QC	Quiescent Current C	EN = HIGH; measurement stopped, SPI communication only		87		µA
I_QD	Quiescent Current D	TDC OFF, counter stopped, no communication		50		µA

7.6 Timing Requirements

		MIN	MAX	UNIT
TIMING REQUIREMENTS: START, STOP INPUTS, CLOCK
PW_START	Pulse width for Start Signal	10		ns
PW_STOP	Pulse width for Stop Signal	10		ns
SERIAL INTERFACE TIMING CHARACTERISTICS (VDD = 3.3 V, f_SCLK = 20 MHz) (See Figure 1)
f_SCLK	SCLK Frequency		20	MHz
t₁	SCLK period	50		ns
t₂	SCLK High Time	16		ns
t₃	SCLK Low Time	16		ns
t₄	DIN setup time	4		ns
t₅	DIN hold time	4		ns
t₆	CSB fall to SCLK rise	6		ns
t₇	Last SCLK rising edge to CSB rising edge	6		ns
t₈	Minimum pause time (CSB high)	40		ns
t₉	Clk fall to DOUT bus transition		12	ns

(1) Accuracy is defined as the systematic error in the output signal; the error of the device excluding noise.

(2) Specified by design.

7.7 Switching Characteristics

T_A = 25°C , VDD = 3.3 V, GND = 0 V (unless otherwise noted).

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
WAKE UP TIME
T_{WAKEUP_PERIOD}	Time to be ready for Measurement	LSB within 0.3% of settled value		300		µs

Figure 1. SPI Register Write: 8 bit Register Example

7.8 Typical Characteristics

T_A = 25°C , VDD = 3.3 V, GND = 0 V, CLOCK = 8 MHz, CALIBRATION2_PERIODS = 10, AVG_CYCLES = 1 Measurement, NUM_STOP = Single STOP, Measurement Mode 2 (unless otherwise noted).