ZHCSJA6B January   2019  – December 2021 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 功能方框图
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Pin Attributes
    3. 7.3 Signal Descriptions
    4. 7.4 Pin Multiplexing
    5. 7.5 Buffer Type
    6. 7.6 Connection of Unused Pins
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 8.5  Typical Characteristics, Active Mode Supply Currents
    6. 8.6  Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
    7. 8.7  Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
    8. 8.8  Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
    9. 8.9  Low-Power Mode (LPMx.5) Supply Currents (Into VCC) Excluding External Current
    10. 8.10 Typical Characteristics, Low-Power Mode Supply Currents
    11. 8.11 Current Consumption per Module
    12. 8.12 Thermal Resistance Characteristics
    13. 8.13 Timing and Switching Characteristics
      1. 8.13.1  Power Supply Sequencing
        1. 8.13.1.1 Brownout and Device Reset Power Ramp Requirements
        2. 8.13.1.2 SVS
      2. 8.13.2  Reset Timing
        1. 8.13.2.1 Reset Input
      3. 8.13.3  Clock Specifications
        1. 8.13.3.1 Low-Frequency Crystal Oscillator, LFXT
        2. 8.13.3.2 High-Frequency Crystal Oscillator, HFXT
        3. 8.13.3.3 DCO
        4. 8.13.3.4 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        5. 8.13.3.5 Module Oscillator (MODOSC)
      4. 8.13.4  Wake-up Characteristics
        1. 8.13.4.1 Wake-up Times From Low-Power Modes and Reset
        2. 8.13.4.2 Typical Wake-up Charges
        3. 8.13.4.3 Typical Characteristics, Average LPM Currents vs Wake-up Frequency
      5. 8.13.5  Digital I/Os
        1. 8.13.5.1 Digital Inputs
        2. 8.13.5.2 Digital Outputs
        3. 8.13.5.3 Typical Characteristics, Digital Outputs
      6. 8.13.6  LEA
        1. 8.13.6.1 Low-Energy Accelerator (LEA) Performance
      7. 8.13.7  Timer_A and Timer_B
        1. 8.13.7.1 Timer_A
        2. 8.13.7.2 Timer_B
      8. 8.13.8  eUSCI
        1. 8.13.8.1 eUSCI (UART Mode) Clock Frequency
        2. 8.13.8.2 eUSCI (UART Mode) Switching Characteristics
        3. 8.13.8.3 eUSCI (SPI Master Mode) Clock Frequency
        4. 8.13.8.4 eUSCI (SPI Master Mode) Switching Characteristics
        5. 8.13.8.5 eUSCI (SPI Master Mode) Timing Diagrams
        6. 8.13.8.6 eUSCI (SPI Slave Mode) Switching Characteristics
        7. 8.13.8.7 eUSCI (SPI Slave Mode) Timing Diagrams
        8. 8.13.8.8 eUSCI (I2C Mode) Switching Characteristics
        9. 8.13.8.9 eUSCI (SPI Slave Mode) Timing Diagrams
      9. 8.13.9  Segment LCD Controller
        1. 8.13.9.1 LCD_C Recommended Operating Conditions
        2. 8.13.9.2 LCD_C Electrical Characteristics
      10. 8.13.10 ADC12_B
        1. 8.13.10.1 12-Bit ADC, Power Supply and Input Range Conditions
        2. 8.13.10.2 12-Bit ADC, Timing Parameters
        3. 8.13.10.3 12-Bit ADC, Linearity Parameters
        4. 8.13.10.4 12-Bit ADC, Dynamic Performance With External Reference
        5. 8.13.10.5 12-Bit ADC, Dynamic Performance With Internal Reference
        6. 8.13.10.6 12-Bit ADC, Temperature Sensor and Built-In V1/2
        7. 8.13.10.7 12-Bit ADC, External Reference
        8. 8.13.10.8 Temperature Sensor Typical Characteristics
      11. 8.13.11 Reference
        1. 8.13.11.1 REF, Built-In Reference
      12. 8.13.12 Comparator
        1. 8.13.12.1 Comparator_E
      13. 8.13.13 FRAM
        1. 8.13.13.1 FRAM Memory
      14. 8.13.14 USS
        1. 8.13.14.1 USS Recommended Operating Conditions
        2. 8.13.14.2 USS LDO
        3. 8.13.14.3 USSXTAL
        4. 8.13.14.4 USS HSPLL
        5. 8.13.14.5 USS SDHS
        6. 8.13.14.6 USS PHY Output Stage
        7. 8.13.14.7 USS PHY Input Stage, Multiplexer
        8. 8.13.14.8 USS_PGA
        9. 8.13.14.9 USS Bias Voltage Generator
      15. 8.13.15 Emulation and Debug
        1. 8.13.15.1 JTAG and Spy-Bi-Wire Interface
  9. 9 Detailed Description
    1. 9.1  Overview
    2. 9.2  CPU
    3. 9.3  Ultrasonic Sensing Solution (USS_A)
    4. 9.4  Low-Energy Accelerator (LEA) for Signal Processing
    5. 9.5  Operating Modes
      1. 9.5.1 Peripherals in Low-Power Modes
      2. 9.5.2 Idle Currents of Peripherals in LPM3 and LPM4
    6. 9.6  Interrupt Vector Table and Signatures
    7. 9.7  Bootloader (BSL)
    8. 9.8  JTAG Operation
      1. 9.8.1 JTAG Standard Interface
      2. 9.8.2 Spy-Bi-Wire Interface
    9. 9.9  FRAM Controller A (FRCTL_A)
    10. 9.10 RAM
    11. 9.11 Tiny RAM
    12. 9.12 Memory Protection Unit (MPU) Including IP Encapsulation
    13. 9.13 Peripherals
      1. 9.13.1  Digital I/O
      2. 9.13.2  Oscillator and Clock System (CS)
      3. 9.13.3  Power-Management Module (PMM)
      4. 9.13.4  Hardware Multiplier (MPY)
      5. 9.13.5  Real-Time Clock (RTC_C)
      6. 9.13.6  Measurement Test Interface (MTIF)
      7. 9.13.7  Watchdog Timer (WDT_A)
      8. 9.13.8  System Module (SYS)
      9. 9.13.9  DMA Controller
      10. 9.13.10 Enhanced Universal Serial Communication Interface (eUSCI)
      11. 9.13.11 TA0, TA1, and TA4
      12. 9.13.12 TA2 and TA3
      13. 9.13.13 TB0
      14. 9.13.14 ADC12_B
      15. 9.13.15 USS_A
      16. 9.13.16 Comparator_E
      17. 9.13.17 CRC16
      18. 9.13.18 CRC32
      19. 9.13.19 AES256 Accelerator
      20. 9.13.20 True Random Seed
      21. 9.13.21 Shared Reference (REF)
      22. 9.13.22 LCD_C
      23. 9.13.23 Embedded Emulation
        1. 9.13.23.1 Embedded Emulation Module (EEM) (S Version)
        2. 9.13.23.2 EnergyTrace++ Technology
    14. 9.14 Input/Output Diagrams
      1. 9.14.1  Port Function Select Registers (PySEL1 , PySEL0)
      2. 9.14.2  Port P1 (P1.0 and P1.1) Input/Output With Schmitt Trigger
      3. 9.14.3  Port P1 (P1.2 to P1.5) Input/Output With Schmitt Trigger
      4. 9.14.4  Port P1 (P1.6 to P1.7) Input/Output With Schmitt Trigger
      5. 9.14.5  Port P2 (P2.0 to P2.1) Input/Output With Schmitt Trigger
      6. 9.14.6  Port P2 (P2.2 to P2.3) Input/Output With Schmitt Trigger
      7. 9.14.7  Port P2 (P2.4 to P2.5) Input/Output With Schmitt Trigger
      8. 9.14.8  Port P2 (P2.6 to P2.7) Input/Output With Schmitt Trigger
      9. 9.14.9  Port P3 (P3.0) Input/Output With Schmitt Trigger
      10. 9.14.10 Port P3 (P3.1) Input/Output With Schmitt Trigger
      11. 9.14.11 Port P3 (P3.2) Input/Output With Schmitt Trigger
      12. 9.14.12 Port P3 (P3.3) Input/Output With Schmitt Trigger
      13. 9.14.13 Port P3 (P3.4 to P3.5) Input/Output With Schmitt Trigger
      14. 9.14.14 Port P3 (P3.6 to P3.7) Input/Output With Schmitt Trigger
      15. 9.14.15 Port P4 (P4.0) Input/Output With Schmitt Trigger
      16. 9.14.16 Port P4 (P4.1 to P4.7) Input/Output With Schmitt Trigger
      17. 9.14.17 Port P5 (P5.0 to P5.7) Input/Output With Schmitt Trigger
      18. 9.14.18 Port P6 (P6.0) Input/Output With Schmitt Trigger
      19. 9.14.19 Port P6 (P6.1 to P6.2) Input/Output With Schmitt Trigger
      20. 9.14.20 Port P6 (P6.3) Input/Output With Schmitt Trigger
      21. 9.14.21 Port P6 (P6.4) Input/Output With Schmitt Trigger
      22. 9.14.22 Port P6 (P6.5 and P6.7) Input/Output With Schmitt Trigger
      23. 9.14.23 Port P7 (P7.0) Input/Output With Schmitt Trigger
      24. 9.14.24 Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger
      25. 9.14.25 Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
      26. 9.14.26 Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger
    15. 9.15 Device Descriptors (TLV)
    16. 9.16 Memory Map
      1. 9.16.1 Peripheral File Map
    17. 9.17 Identification
      1. 9.17.1 Revision Identification
      2. 9.17.2 Device Identification
      3. 9.17.3 JTAG Identification
  10. 10Applications, Implementation, and Layout
    1. 10.1 Device Connection and Layout Fundamentals
      1. 10.1.1  Power Supply and Bulk Capacitors
      2. 10.1.2  External Oscillator (HFXT and LFXT)
      3. 10.1.3  USS Oscillator (USSXT)
      4. 10.1.4  Transducer Connection to the USS Module
      5. 10.1.5  Charge Pump Control of Input Multiplexer
      6. 10.1.6  JTAG
      7. 10.1.7  Reset
      8. 10.1.8  Unused Pins
      9. 10.1.9  General Layout Recommendations
      10. 10.1.10 Do's and Don'ts
    2. 10.2 Peripheral- and Interface-Specific Design Information
      1. 10.2.1 ADC12_B Peripheral
        1. 10.2.1.1 Partial Schematic
        2. 10.2.1.2 Design Requirements
        3. 10.2.1.3 Detailed Design Procedure
        4. 10.2.1.4 Layout Guidelines
      2. 10.2.2 LCD_C Peripheral
        1. 10.2.2.1 Partial Schematic
        2. 10.2.2.2 Design Requirements
        3. 10.2.2.3 Detailed Design Procedure
        4. 10.2.2.4 Layout Guidelines
  11. 11Device and Documentation Support
    1. 11.1 Getting Started
    2. 11.2 Device Nomenclature
    3. 11.3 Tools and Software
    4. 11.4 Documentation Support
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 术语表
    9. 11.9 Export Control Notice
  12. 12Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

1 特性

  • 功耗超低的一流超声波水流和气流测量
    • 水
      • 在低流速到高流速的情况下以及工作温度范围内的差分飞行时间 (dToF) 精度为 ±12.5ps
      • 可在 500:1 的宽动态范围内实现 ±1% 精度
      • 在直径为 25mm 的管道上，能够测量的最大流速为 8800 升/小时（40 加仑/分钟）
      • 能够检测的最小流速小于 1 升/小时（0.005 加仑/分钟）
      • 高精度时间测量分辨率小于 5ps
      • 在每秒获取一组结果的条件下总体电流消耗大约为 3µA
      • 能够支持直径为 15mm 至 1000mm 的宽管道尺寸
    • 气体
      • 在低流速到高流速的情况下以及工作温度范围内的差分飞行时间 (dToF) 精度为 ±250ps
      • 可在流速高达 12000 升/小时的条件下实现 ±1% 的精度，具有 200:1 的宽动态范围
      • 能够测量的流速大于 25000 升/小时
      • 能够检测的最小流速小于 3 升/小时
      • 高精度时间测量分辨率小于 100ps
      • 在每秒获取一组结果的条件下总体电流消耗大约为 20µA
  • 符合并超出 ISO4064、OIML R49、EN 14236 和 EN 1434 精度标准
  • 能够直接与标准超声波传感器（高达 2.5MHz）连接
  • 集成模拟前端 – 超声波传感解决方案 (USS_A)，包括
    • 用于在各种频率下生成多音调脉冲的可编程脉冲发生器 (PPG)
    • 用于控制输入和输出通道且具有低阻抗输出驱动器 (4Ω) 的集成 PHY
    • 具有高达 8Msps 输出数据速率的高性能高速 12 位模数转换器 (SDHS)
    • 具有 –6.5dB 至 30.8dB 增益的可编程增益放大器 (PGA)
    • 输出范围为 68MHz 至 80MHz 的高性能 PLL
  • 计量测试接口 (MTIF)
    • 脉冲发生器和脉冲计数器
    • 脉冲率高达 1024 次脉冲/秒 (p/s)
    • 计数容量高达 65535（16 位）
    • 在 LPM3.5 下以 200nA（典型值）运行
  • 低功耗加速器 (LEA)
    • 独立于 CPU 运行
    • 与 CPU 共享 8KB RAM
    • 高效的 256 点复数 FFT：比 Arm®Cortex®-M0+ 内核最多快 40 倍
  • 嵌入式微控制器
    • 时钟频率高达 16MHz 的 16 位精简指令集计算机 (RISC) 架构
    • 宽电源电压范围：1.8V 至 3.6V (1)
  • 优化的超低功耗模式
    • 激活模式：大约 120 µA/MHz
    • 具有实时时钟 (RTC) 的待机模式 (LPM3.5)：450nA (2)
    • 关断 (LPM4.5)：30nA
  • 铁电随机存取存储器 (FRAM)
    • 容量高达 64KB 的非易失性存储器
    • 超低功耗写入
    • 以 125ns/字（4ms 内写入 64KB）的速度快速写入
    • 统一的存储器 = 程序 + 数据 + 存储都处于同一存储空间
    • 耐写次数达 1015 次
    • 抗辐射和非磁性
  • 智能数字外设
    • 32 位硬件乘法器 (MPY)
    • 6 通道内部 DMA
    • 带有日历和报警功能的 RTC
    • 6 个 16 位计时器，每个计时器具有多达 7 个捕捉/比较寄存器
    • 32 位和 16 位循环冗余校验 (CRC)
  • 高性能模拟
    • 12 通道模拟比较器
    • 12 位 ADC，具有窗口比较器、内部基准和采样保持功能以及多达 8 条外部输入通道
    • 具有高达 248 段对比度控制的集成 LCD 驱动器
  • 多功能输入/输出端口
    • 所有引脚均支持电容式触控功能，无需外部组件
    • 可按位、字节和字进行访问（成对访问）
    • 所有端口均可从 LPM 进行边沿可选唤醒
    • 所有端口均具有可设定的上拉电阻或下拉电阻
  • 代码安全性和加密
    • 128 位或 256 位 AES 安全加密和解密协处理器
    • 用于随机数生成算法的随机数种子
    • IP 封装可保护存储器免遭外部访问
    • FRAM 可提供固有安全性优势
  • 增强型串行通信
    • 多达 4 个 eUSCI_A 串行通信端口
      • 支持自动波特率检测的 UART
      • IrDA 编码和解码
    • 多达 2 个 eUSCI_B 串行通信端口
      • 支持多从器件寻址的 I2C
    • 硬件 UART 或 I2C 引导加载程序 (BSL)
  • 灵活的时钟系统
    • 具有 10 个可选厂家调整频率的固定频率数控振荡器 (DCO)
    • 低功耗低频内部时钟源 (VLO)
    • 32kHz 晶振 (LFXT)
    • 高频晶振 (HFXT)
  • 开发工具和软件
  • 器件比较汇总了可用的器件型号和封装选项
1. 最低电源电压受限于 SVS 电平（请参阅 SVS 规格）
2. RTC 由 3.7pF 晶振计时。