DAC8775 クワッド・チャネル、16ビット、プログラマブル電流出力および電圧出力 デジタル/アナログ・コンバータ、適応型電力管理機能搭載

8.3.1 Current Output Stage

Each channel's current output stage consists of a pre-conditioner and a precision current source as shown in Figure 101. This stage provides a current output according to the DAC code. The output range can be programmed as 0 mA to 20 mA, 0 mA to 24 mA, 4 mA to 20 mA, 3.5 mA to 23.5 mA, or ±24 mA. In the current output mode, the maximum compliance voltage on pin IOUT_x is between (-|VNEG_IN_x| + 3 V) ≤ |IOUT_x| ≤ (VPOS_IN_x – 3 V). This compliance voltage is automatically maintained when the Buck-Boost converter is used to generate these supplies (see Buck-Boost Converter section). However, when using an external supply for VPOS_IN_x pin (Buck-Boost converter disabled), the VPOS_IN_x and VNEG_IN_x supplies should be chosen such that this compliance voltage is maintained.

Figure 101. Current Output

The 16 bit data can be written to DAC8775 using address 0x05 (DAC data registers, see Table 5 and Table 6).

For a 0-mA to 20-mA output range:

Equation 1.

For a 0-mA to 24-mA output range:

Equation 2.

For a 3.5-mA to 23.5-mA output range:

Equation 3.

For a 4-mA to 20-mA output range:

Equation 4.

For a -24-mA to 24-mA output range:

Equation 5.

Where:

• CODE is the decimal equivalent of the code loaded to the DAC.
• N is the bits of resolution; 16.

8.3.2 Voltage Output Stage

The voltage output stage as conceptualized in Figure 102 provides the voltage output according to the DAC code and the output range setting. The output range can be programmed as 0 V to +5 V or 0 V to +10 V for unipolar output mode, and ±5 V or ±10 V for bipolar output mode. In addition, an option is available to increase the output voltage range by 20%. The output current drive can be up to 10 mA. The output stage has short-circuit current protection that limits the output current to 16 mA, this limit can be changed to 8 mA, 20 mA or 24mA via writing bits 15 and 14 of address 0x04. This minimum headroom and footroom for the voltage output stage is automatically maintained when the Buck-Boost converter is used to generate these supplies. However, when using an external supply for VPOS_IN_x and VNEG_IN_x pin (Buck-Boost converter disabled) the minimum headroom and footroom as per must be maintained. In this case, the Recommended Operating Conditions shows the maximum allowable difference between VPOS_IN_x and VNEG_IN_x.

The voltage output is designed to drive capacitive loads of up to 1 μF. For loads greater than 20 nF, an external compensation capacitor can be connected between CCOMP_x and VOUT_x to keep the output voltage stable at the expense of reduced bandwidth and increased settling time. Note that, a step response (due to input code change) on the voltage output pin loaded with large capacitive load (> 20 nF) will trigger the short circuit limit circuit of the output stage. This will result in setting the short circuit alarm status bits. Therefore, it is recommended to use slew rate control for large step change, when the voltage output pin is loaded with high capacitive loads.

Figure 102. Voltage Output

The VSENSEP_x pin is provided to enable sensing of the load. Ideally, it is connected to VOUT_x at the terminals. Additionally, it can also be used to connect remotely to points electrically "nearer" to the load. This allows the internal output amplifier to ensure that the correct voltage is applied across the load as long as headroom is available on the power supply. However, if this line is cut, the amplifier loop would be broken. Therefore, an optional resistor can be used between VOUT_x and VSENSEP_x to prevent this.

The VSENSEN_x pin can be used to sense the remote ground and offset the VOUT pin accordingly. The VSENSEN_x pin can sense a maximum of ±7 V difference from the PBKG pin of the DAC8775.

The 16-bit data can be written to DAC8775 as shown in DAC data registers, see Table 5 and Table 6.

For unipolar output mode:

Equation 6.

For bipolar output mode:

Equation 7.

Where:

• CODE is the decimal equivalent of the code loaded to the DAC.
• N is the bits of resolution; 16.
• VREFIN is the reference voltage; for internal reference, VREFIN = +5 V.
• GAIN is automatically selected for a desired voltage output range as shown in Table 7.

8.3.3 Buck-Boost Converter

The DAC8775 includes a Buck-Boost Converter for each channel to minimize the power dissipation of the chip and provides significant system integration. This Buck-Boost converter is based on a Single Inductor Multiple Output (SIMO) architecture and requires a single inductor (per channel) to simultaneously generate all the analog power supplies required by the chip. The Buck-Boost converters utilize three on-chip switches (shown in Figure 103) which are synchronously controlled via current mode control logic. These converters are designed to work in discontinuous conduction mode (DCM) with an external inductor (per channel) of value 100 µH connected between LN_x and LP_x pins (see Buck-Boost Converter External Component Selection section). The peak inductor current inductor is limited to a value of 0.5 A internally.

Figure 103. Buck-Boost Converter

These Buck-Boost converters employ a variable switching frequency technique. This technique increases the converter efficiency at all loads by automatically reducing the switching frequency at light loads and increasing it at heavy loads. At no load condition, the converter stops switching completely until the load capacitor discharges by a preset voltage. At this point the converter automatically starts switching and recharges the load capacitor(s). In addition to saving power at all loads, this technique ensures low switching noise on the converter outputs at light loads. The minimum load capacitor for these Buck-Boost converters is 10 µF. This capacitor must be connected between the schottky diode(s) and ground (0 V) for each arm of each Buck-Boost converter (A, B, C, D). The Buck-Boost converter, when enabled, generates ripple on the supply pins (VPOS_IN_x and VNEG_IN_x). This ripples is typically attenuated by the power supply rejection ratio of the output amplifiers (IOUT_x or VOUT_x) and appears as noise on the output pin of the amplifiers (IOUT_x and VOUT_x). A larger load capacitor in combination with additional filter (see Application Information section) reduces the output ripple at the expense of increasing settling time of the converter output.

The input voltage to the Buck-Boost converters (pin PVDD_x) can vary from +12 V to +36 V. These outputs can be individually enabled or disabled via the user SPI interface (see Commands in Table 5 and Table 6).

8.3.3.1 Buck-Boost Converters Outputs

Each of the four Buck-Boost converters can be used to provide power to the current output stage or the voltage output stage by enabling the respective Buck-Boost converter and connecting the power supplies as shown in Figure 104. Additional passive filters can optionally be added between the schottky diode and input supply pins (VPOS_IN_x and VNEG_IN_x) to attenuate the ripple feeding into the VPOS_IN_x and VNEG_IN_x pin.

Figure 104. Buck-Boost Converter Positive and Negative Outputs

8.3.4 Analog Power Supply

After power up it is required that a hardware reset is issued using the RESET pin.

The DAC8775 is design to operate with a single power supply (12 V to 36 V) using integrated Buck-Boost converter. In this mode, pins PVDD_x and AVDD must be tied together and driven by the same power supply. VPOS_INx and VNEG_IN_x will be enabled as programmed by the device registers. It is recommended that DVDD is applied first to reduce output transients.

The DAC8775 can also be operated without using the integrated Buck-Boost converter. In this mode, pins PVDD_x, AVDD, and VPOS_IN_x must be tied together and driven by the same power supply (12 V to 36 V). In this mode in order to reduce output transients it is recommended that DVDD is applied first, followed by VPOS_IN_x / PVDD_x / AVDD and finally REFIN. Note that in this mode, the minimum required head room and foot room for the output amplifiers must be met.

Recommended Operating Conditions shows the maximum and minimum allowable limits for all the power supplies when DAC8775 is powered using external power supplies.

8.3.5 Digital Power Supply

The digital power supply to DAC8775 can be internally generated or externally supplied. This is determined by the status of DVDD_EN pin.

When the DVDD_EN pin is left floating, the voltage on DVDD pin is generated via an internal LDO. The typical value of the voltage generated on DVDD pin is 5 V. In this mode, the DVDD pin can also be used to power other digital components on the board. The maximum drive capability of this pin is 10mA. Please note that to ensure stability the minimum load capacitance on this pin is limited to 100 pF, where as the maximum load capacitance is limited to 0.1 µF.

When the DVDD_EN pin is tied to 0 V, the internal LDO is disabled and the DVDD pin must be powered via an external digital supply.

8.3.6 Internal Reference

The DAC8775 includes an integrated 5-V reference with an initial accuracy of ±10 mV maximum and a temperature drift coefficient of 10 ppm/°C maximum. A buffered output capable of driving up to 5 mA is available on REFOUT. The internal reference for DAC8775 is disabled by default. To enable the internal reference, REF_EN bit on address 0x02h must be set to '1' (see Table 6).

8.3.7 Power-On-Reset

The DAC8775 contain power on reset circuits which is based on AVDD and DVDD power supplies. After power-on, the power-on-reset circuit ensures that all registers are at their default values (see Table 5). The current, voltage output DACs, and the Buck-Boost converters are disabled. The current output pin is in high impedance state.

The voltage output pin is in a 30kΩ-to-GND state; however, the VSENSEP_x pin is an open circuit. The voltage output pin impedance may be changed to high-impedance by the POC bit setting.

8.3.8 ALARM Pin

The DAC8775 contains an ALARM pin. When one or more of following events occur, the ALARM pin is pulled low:

1. The load on any channel's IOUT_x pin is in open circuit (> 500 µsec); or
2. The voltage at IOUT_x, when enabled, reaches a level where the accuracy of the output current would be compromised. This condition is detected by monitoring internal voltage levels of the IOUT_x circuitry and will typically be below the specified compliance voltage minimum of 3 V (> 500 µsec). Note that, when the buck boost converter is enabled in full tracking mode (CCLP[1:0] = "00"), a transient alarm signal can be observed during the current output transition. This condition occurs because the compliance voltage for current output is violated as the buck boost converter is adjusting the power supply. Alternatively the alarm can be programmed to only indicate an alarm once the DC/DC has reached saturation and the compliance voltage condition is still being violated; or
3. The die temperature has exceeded +150°C; or
4. The SPI watchdog timer exceeded the timeout period (if enabled); or
5. The SPI frame error check (CRC) encountered an error (if enabled).
6. A short circuit current limit is reached (> 500 µsec) on any VOUT_x when enabled in voltage output mode.
7. The Buck-Boost converter has reached the maximum output voltage (set by bit HSCLMP, Table 6 address 0x0E).

When connecting the ALARM pins of multiple DAC8775 devices together, forming a wired-AND function, the host processor should read the status register of each device to know all the fault conditions that are present.

The ALARM pin continuously monitors the above mentioned conditions and returns to open drain condition if the alarm condition is removed (non-latched behavior - default). For condition (1) mentioned above and Buck-Boost converter used to power the DAC, the ALARM pin if pulled low due to the alarm condition will remain pulled low even after the alarm condition is removed (latched behavior). In this condition the alarm pin can be reset by

1. Resetting the corresponding fault bits in the status register (address 0x0B, Table 6); or
2. Performing software reset (write to address 0x01, Table 6); or
3. Toggling hardware reset pin; or
4. Performing power on reset.

Note that if the alarm action bits are programmed to "10" (AC_IOC[1:0], the Buck-Boost converter and the current output amplifier are automatically disabled upon the event of open circuit on current output. In this case, the ALARM automatically resets to the default behavior (non-latched behavior).

8.3.9 Power GOOD Bits

Each Buck-Boost converter in DAC8775 has a read only bit called power good (PGx) (address 0x0B, Table 6). This bit is set to logic '1' when both of the following conditions are met:

1. The VPOS_IN_x > 4 V (if enabled) and
2. The VNEG_IN_x < –3 V (if enabled)

The PGx bit indicates the status of the outputs of the enabled Buck-Boost converters. For example if the output of Buck-Boost converter A is the only one enabled, then the PGA bit will be set to a logic '1' only after the positive output pins of the Buck-Boost converter A are ≥ 3.0 V and the negative output pin of Buck-boost converter A is ≤ -3.0 V.

8.3.10 Status Register

Since, DAC8775 contains one ALARM pin for the entire chip, the status of individual fault condition can be checked using the status register. This register (see Register Maps and Bit Functions section) consists of five types of ALARM status bits (Faults on current and voltage outputs , Over temperature condition, CRC errors, Watchdog timeout and Buck-Boost converter power good) and two status bit (User toggle, Auto Learn status). The device continuously monitors these conditions. When an alarm occurs, the ALARM pin is pulled low and the corresponding status bit is set ('1'). Whenever one of these status bits is set, it remains set until the user clears it by writing '1' to corresponding bit on address 0x0B. The status bit can also be cleared by performing a hardware reset, software reset, or power-on reset, note that it takes a minimum of 8 µsec for the status register to get reset. These bits are reasserted if the ALARM condition continues to exist in the next monitoring cycle.

8.3.11 Status Mask

The ALARM pin for DAC8775 is triggered by any of the alarm conditions (see ALARM Pin section). However, these different alarm conditions can be masked from creating the alarm signal at the pin by using the status mask register. The status mask register (address 0x0C, Table 6) has the same bit order as the status register except that it can be set to mask any or all status bits that create the alarm signal.

8.3.12 Alarm Action

The DAC8775 implements an alarm action register (address 0x0D,Table 6). By writing to this register, the user can select the action that the device will take automatically in case of a specific alarm condition. In case, different setting are chosen for different alarm conditions, the following priority (high to low) will be considered when taking action:

1. Over temperature alarm
2. Output fault alarm
3. CRC error/Watchdog timer fault alarm

This device also contains a 6-bit alarm code register (address 0x0E, Table 6) which can be loaded to the DACs if the alarm action register is set to "01". Note that the alarm code, once set, remains set even if the alarm condition is removed. Also note that the alarm action change to the programmed code is a step function even if slew rate control is enabled.

8.3.13 Watchdog Timer

This feature is useful to ensure that communication between the host processor and the DAC8775 has not been lost. It can be enabled by setting the WEN (address 0x03) bit to '1', see Table 6. The watchdog timeout period can be set using the WPD[1:0] address 0x03) bits. The timer period is based off an internal oscillator with a typical value of 8 MHz.

If enabled, the chip must have an SPI frame with 0x10 as the write address byte written to the device within the programmed timeout period. Otherwise, the ALARM pin asserts low and the WDT bit (address 0x0B) of the status register is set to '1'. The WDT bit is set to '0' with a software/hardware reset, or by disabling the watchdog timer (WEN = '0'), or powering down the device.

When using multiple DAC8775 devices in a daisy-chain configuration, the open-drain ALARM pins of all devices can be connected together to form a wired-AND network. The watchdog timer can be enabled in any number of the devices in the chain although enabling it in one device in the chain should be sufficient. The wired-AND ALARM pin may get pulled low because of the simultaneous presence of different trigger conditions in the devices in the daisy-chain. The host processor should read the status register of each device to know all the fault conditions present in the chain.

8.3.14 Programmable Slew Rate

The slew rate control feature allows the user to control the rate at which the output voltage or current changes. This feature is disabled by default and can be enabled for the selected channel by writing logic '1' to the SREN bit at address 0x04 (see Table 6). With the slew rate control feature disabled, the output changes smoothly at a rate limited by the output drive circuitry and the attached load.

With this feature enabled, the output does not slew directly between the two values. Instead, the output steps digitally at a rate defined by bits [2:0] (SR_STEP) and bits [3:0] (SRCLK_RATE) on address 0x04 (see Table 6). SR_RATE defines the rate at which the digital slew updates; SRCLK_STEP defines the amount by which the output value changes at each update. Table 6 shows different settings for SRCLK_STEP and SR_RATE.

The time required for the output to slew over a given range can be expressed as Equation 8:

Equation 8.

Where:

• Slew Time is expressed in seconds
• Output Change is expressed in amps (A) for current output mode or volts (V) for voltage output mode

When the slew rate control feature is enabled, the output changes happen at the programmed slew rate. This configuration results in a staircase formation at the output. If the CLR pin is asserted, the output slews to the zero-scale value at the programmed slew rate. When a new DAC data is written, the output starts slewing to the new value at the slew rate determined by the current DAC code and the new DAC data. The update clock frequency for any given value is the same for all output ranges. The step size, however, varies across output ranges for a given value of step size because the LSB size is different for each output range.

Note that disabling the slew rate feature while the DAC is executing the slew rate command will abort the slew rate operation and the DAC output will stay at the last code after which the slew rate disable command was acknowledged.

8.3.15 HART Interface

On the DAC8775, digital communication such as HART can be modulated onto the input signal for each channel.

In the case where the RANGE (address 0x04) bits are programmed such that the IOUT_x is enabled, the external HART signal (ac voltage; 500 mV_PP, 1200 Hz and 2200 Hz) can be capacitively coupled in through the HARTIN_x pin and transferred to a current that is superimposed on the current output. The HARTIN_x pin has a typical input impedance of 20 kΩ to 30 kΩ, depending on the selected current output range, which together with the input capacitor used to couple the external HART signal into the HARTIN_x pin can be used to form a high-pass filter to attenuate frequencies below the HART bandpass region. In addition to this filter, an external passive filter is recommended to complete the filtering requirements of the HART specifications. Figure 105 illustrates the output current versus time operation for a typical HART interface.

NOTE:

DC current = 6 mA.

Figure 105. Output Current vs Time

The HART pin for the selected channel can be enabled by writing logic '1' to the HTEN bit at address 0x04 (see Table 5 and Table 6).

8.4.1 Serial Peripheral Interface (SPI)

The device is controlled over a versatile four-wire serial interface (SDIN, SDO, SCLK, and SYNC) that operates at clock rates of up to 25 MHz and is compatible with SPI, QSPI™, Microwire™, and digital signal processing (DSP) standards. The SPI communication command consists of a write address byte and a data word for a total of 24 bits (when CRC is disabled). The timing for the digital interface is shown in the Timing Requirements: Write and Readback Mode section.

8.4.1.2 Daisy-Chain Operation

For systems that contain more than one device, the SDO pin can be used to daisy-chain multiple devices together. Daisy-chain operation can be useful for system diagnostics and in reducing the number of serial interface lines. The daisy chain feature can be enabled by writing logic '0' to DSDO bit address 0x03 (see Table 6), the SDO pin is set to HiZ when DSDO bit is set to 1. By connecting the SDO of the first device to the SDIN input of the next device in the chain, a multiple-device interface is constructed, as Figure 11 illustrates.

Figure 106. Three DAC8775s in Daisy-Chain Mode

The DAC8775 provides two modes for daisy-chain operation: normal and transparent. The TRN bit in the Reset config register determines which mode is used. In Normal mode (TRN bit = '0'), the data clocked into the SDIN pin are transferred into the shift register. The first falling edge of SYNC starts the operating cycle. SCLK is continuously applied to the SPI Shift Register when SYNC is low. If more than 24 clock pulses are applied, the data ripple out of the shift register and appear on the SDO line. These data are clocked out on the rising edge of SCLK and are valid on the falling edge. By connecting the SDO pin of the first device to the SDIN input of the next device in the chain, a multiple-device interface is constructed. Each device in the system requires 24 clock pulses. Therefore, the total number of clock cycles must equal 24 × N, where N is the total number of DAC8775s in the chain. When the serial transfer to all devices is complete, SYNC is taken high. This action latches the data from the SPI Shift registers to the device internal registers synchronously for each device in the daisy-chain, and prevents any further data from being clocked in. Note that a continuous SCLK source can only be used if SYNC is held low for the correct number of clock cycles. For gated clock mode, a burst clock containing the exact number of clock cycles must be used and SYNC must be taken high after the final clock in order to latch the data.

In Transparent mode (address 0x02h, TRN bit = '1' Table 6), the data clocked into SDIN are routed to the SDO pin directly; the Shift Register is bypassed. When SCLK is continuously applied with SYNC low, the data clocked into the SDIN pin appear on the SDO pin almost immediately (with approximately a 12 ns delay); there is no 24 clock delay, as there is in normal operating mode. While in Transparent mode, no data bits are clocked into the Shift Register, and the device does not receive any new data or commands. Putting the device into transparent mode eliminates the 24 clock delay from SDIN to SDO caused by the Shift Register, thus greatly speeding up the data transfer. For example, consider three DAC8775s (C, B, and A) in a daisy-chain configuration (see Figure 11). The data from the SPI controller are transferred first to C, then to B, and finally to A. In normal daisy-chain operation, a total of 72 clocks are needed to transfer one word to A. However, if C and B are placed into Sleep mode, the first 24 data bits are directly transferred to A (through C and B); therefore, only 24 clocks are needed.

To wake the device up from transparent mode and return to normal operation, the hardware RESET pin must be toggled.

8.4.2 SPI Shift Register

The SPI Shift Register is 24 bits wide (refer to the Frame Error Checking section for 32-bit frame mode). The default 24-bit input frame consists of an 8-bit address byte followed by a 16-bit data word as shown in Table 2.

8.4.3 Write Operation

A typical write to program a channel of the DAC8775 consists of writing to the following registers in the sequence shown in Figure 12.

Figure 107. Typical Write to DAC8775

8.4.4 Read Operation

A read operation is accomplished when DB 23 is '1' (see Table 3). A no-operation (NOP) command should follow the read operation in order to clock out an addressed register. The read register value is output MSB first on SDO on successive falling edges of SCLK.

8.4.5 Updating the DAC Outputs and LDAC Pin

Depending on the status of both SYNC and LDAC, and after data have been transferred into the DAC Data registers, the DAC outputs can be updated either in asynchronous mode or synchronous mode.

8.4.6 Hardware RESET Pin

When the RESET pin is low, the device is in hardware reset. All the analog outputs (VOUT_A to VOUT_D and IOUT_A to IOUT_D), all the registers except the POC register, and the DAC latches are set to the default reset values. In addition, the Gain and Zero registers are loaded with default values, communication is disabled, and the signals on SYNC and SDIN are ignored (note that SDO is in a high-impedance state). When the RESET pin is high, the serial interface returns to normal operation and all the analog outputs (VOUT_A to VOUT_D and IOUT_A to IOUT_D) maintain the reset value until a new value is programmed.

8.4.7 Hardware CLR Pin

The CLR pin is an active high input that should be low for normal operation. When this pin is a logic '1', all the outputs are cleared to either zero-scale code or midscale code depending on the status of the CLSLx bit (see Reset Register (address = 0x01) [reset = 0x0000]). While CLR is high, all LDAC pulses are ignored. When CLR is taken low again, the DAC outputs remain cleared until new data is written to the DACs. The contents of the Offset registers, Gain registers, and DAC input registers are not affected by taking CLR high. Note that the clear action will result in the outputs clearing to the default value instantaneously even if slew rate control is enabled.

8.4.8 Frame Error Checking

If the DAC8775 is used in a noisy environment, error checking can be used to check the integrity of SPI data communication between the device and the host processor. This feature can be enabled by setting the CREN bit address 0x03 (see Table 6).

The frame error checking scheme is based on the CRC-8-ATM (HEC) polynomial x⁸ + x² + x + 1 (that is, 100000111). When error checking is enabled, the SPI frame width is 32 bits, as shown in Table 1. The normal 24-bit SPI data are appended with an 8-bit CRC polynomial by the host processor before feeding it to the device. For a register readback, the CRC polynomial is output on the SDO pins by the device as part of the 32 bit frame.

Note that the user has to start with the default 24 bit frame and enable frame error checking through the CREN bit and switch to the 32 bit frame. Alternatively, the user can use a 32-bit frame from the beginning and pad the 8 MSB bits as the device will only use the last 24 bits until the CRCEN bit is set. The frame length has to be carefully managed, especially when using daisy-chaining in combination with CRC checking to ensure correct operation.

The DAC8775 decodes the 32-bit input frame data to compute the CRC remainder. If no error exists in the frame, the CRC remainder is zero. When the remainder is non-zero (that is, the input frame has single- or multiple-bit errors), the ALARM pin asserts low and the CRE bit of the status register (address 0x0B) is also set to '1'. Note that the ALARM pin can be asserted low for any of the different conditions as explained in the ALARM Pin section. The CRE bit is set to '0' with a software or hardware reset, or by disabling the frame error checking, or by powering down the device. In the case of a CRC error, the specific SPI frame is blocked from writing to the device.

Frame error checking can be enabled for any number of DAC8775 devices connected in a daisy-chain configuration. However, it is recommended to enable error checking for none or all devices in the chain. When connecting the ALARM pins of all combined devices, forming a wired-AND function, the host processor should read the status register of each device to know all the fault conditions present in the chain. For proper operation, the host processor must provide the correct number of SCLK cycles in each frame, taking care to identify whether or not error checking is enabled in each device in the daisy-chain.

8.4.9 DAC Data Calibration

Each channel of the DAC8775 contains a dedicated user calibration register set. This feature allows the user to trim the system gain and offset errors. Both the voltage output and the current output have common user calibration registers available. The user calibration feature is disabled by default. To enable this feature for a selected channel(s), the CLEN bit (DB0) on address 0x08 must be set to logic '1 (see Table 6).

8.4.9.1 DAC Data Gain and Offset Calibration Registers

The DAC calibration register set includes one gain calibration and one offset calibration register (16 bits for DAC8775) per channel (address 0x09 and 0x0A). The range of gain adjustment is typically ±50% of full-scale with 1 LSB per step. The power-on value of the gain register is 0x8000 which is equivalent to a gain of 1. The offset code adjustment is typically ±32,768 LSBs with 1 LSB per step. The input data format of the gain register is unsigned straight binary, and the input data format of the offset register is twos complement. The gain and offset calibration is described by Equation 9.

Equation 9.

Where:

• CODE is the decimal equivalent of the code loaded to the DAC.
• VREFIN is the reference voltage; for internal reference, VREFIN = +5 V.
• GAIN is automatically selected for a desired voltage output range as shown in Table 7.
• User_Offset is the signed 16-bit code in the offset register.
• User_GAIN is the unsigned 16-bit code in the gain register.

It is important to note that this is a purely digital implementation and the output is still limited by the programmed value at both ends of the voltage or current output range. Therefore, the user must remember that the correction only makes sense for endpoints inside of the true device end points. If the user desires to correct more than just the actual device error, for example a system offset, the valid range for the adjustment would change accordingly and must be taken into account. This range is set by the RANGE bits as described in Table 6.

8.5.1 DAC8775 Commands

Note that, in order to write to (or read from) a per channel address, corresponding Buck-Boost converter and DAC channel must be selected using commands 0x06 and 0x03.

8.5.2 Register Maps and Bit Functions

9.1.1 Buck-Boost Converter External Component Selection

Figure 127. DAC8775 External Buck-Boost Components with Recommended Values

The buck-boost converters integrated in the DAC8775 each require three external passive components for operation: a single inductor per channel as well as storage capacitors and switching diodes for each VPOS_IN_x and VNEG_IN_x channels that are active. If only one output is used, either VPOS_IN_x or VNEG_IN_x, the inactive output components may be removed and the respective inputs tied to ground. In order to meet the parametric performance outlined in the Electrical Characteristics section for the voltage output, 500 mV of foot-room is required on VNEG_IN_x.

The recommended value for the external inductor is 100 µH with at least 500 mA peak inductor current. Reducing the inductor value to as low as 80 µH is possible, though this will limit the buck-boost converter maximum input voltage to output voltage ratio, reduce efficiency, and increase ripple. Reducing the inductor below 80 µH will result in device damage. Peak inductor current should be rated at 500 mA or greater with 20% inductance tolerance at peak current. If peak inductor current for an inductor is violated the effective inductance is reduced, which will impact maximum input to output voltage ratio, efficiency, and ripple.

An output, or storage, X7R capacitor with value of 10 µF and voltage rating of 50 V is recommended though other values and dielectric materials may be used without damaging the DAC8775. Reducing capacitor value will increase buck-boost converter output ripple and reduced voltage rating will reduce effective capacitance at full-scale buck-boost converter outputs. X7R capacitors are rated for –55°C to 125°C operation with 15% maximum capacitance variance over temperature. Designs operating over reduced temperature spans and with loose efficiency requirements may use different dielectric material. C0G capacitor typically offer tighter capacitance variance but come in larger packages, but may be beneficial substitutes.

The external diode switches illustrated on the left and right side of the 100 µH inductor shown in Figure 127 should be selected based on reverse voltage rating, reverse recovery time, leakage or parasitic capacitance, and current or power ratings. Breakdown voltage rating of at least 60 V is recommended to accommodate for the maximum voltage that may be across the diode when both VPOS_x and VNEG_x are both active during switching of the DC/DCs. Minimal reverse recovery time and parasitic capacitance is recommended in order to preserve efficiency of the DC/DCs. The external diode should be rated for at least 500 mA average forward current.

9.1.2 Voltage and Current Ouputs on a Shared Terminal

Figure 128 illustrates a simplified block diagram of the voltage output stages of the DAC8775.

Figure 128. Simplified Block Diagram of Voltage Output Architecture

When designing for a shared voltage and current output terminal it is important to consider leakage paths that may corrupt the voltage or current output stages.

When the voltage output is active and the current output is inactive the IOUT_x pin becomes a high-impedance node and therefore does not significantly load the voltage output in a way that would degrade VOUT_x performance. When the voltage output is inactive and the current output is active switches S1, S2, and S4 all become open while switch S3 is controlled by the POC bit in the Reset Config Register for each respective channel. When the POC bit is set to a 0, the default value, switch S3 is closed when VOUT is disabled. This creates a leakage path with respect to the current output when the terminals are shared which will create a load-dependent error. In order to reduce this error the POC bit can be set to a 1 which opens switch S3, effectively making the VOUT pin high-impedance and reducing the magnitude of leakage current.

9.1.3 Optimizing Current Output Settling time with Auto learn Mode

When the buck-boost converters are active power and heat dissipation of the device are at a minimum, however settling time of the current output is dominated by the slew rate of the buck-boost converter, which is significantly slower that the current output signal chain alone. When the buck-boost converters are bypassed settling time of the current output is minimized while power and heat dissipation are significant.

Auto-learn mode offers an alternative mode which allows the buck-boost converter to learn the size of the load and choose a clamped output value that does not change over the full range of the selected current output. This allows a balance between settling time and power dissipation. There are two options for entering auto-learn mode:

• Enable the buck-boost converter in full-tracking mode followed by enabling the current output. Until the DAC code 0x4000 is passed, settling time will be dominated by the buck-boost converter. After code 0x400 is surpassed the buck-boost converter detects the load and sets the clamp value appropriately.
• Enable the buck-boost converter in clamp-mode with clamp value set to a greater voltage than required by the largest load the current output will be expected to drive, followed by enabling the current output. Enter full-tracking mode. In this case the clamp value of maintained without the buck-boost converter output changing, therefore settling time is set by the IOUT_x signal chain. After code 0x4000 is surpassed the buck-boost converter detects the load and adjusts the clamp value appropriately. At all times using this initialization procedure the settling time is defined by the IOUT_x signal chain.

9.1.4 Protection for Industrial Transients

In order to successfully protect the DAC8775, or any integrated circuit, against industrial transient testing the internal structures and how they may behave when exposed to said signals must be understood. Figure 129 depicts a simplified representation of internal structures present on the device’s output pins which are represented as a pair of clamp-to-rail diodes connected to the VPOS_IN_x and VNEG_IN_x supply rails.

Figure 129. Simplified Block Diagram of Internal Structures and External Protection

When these internal structures are exposed to industrial transient testing, without the external protection components, the diode structures will become forward biased and conduct current. If the conducted current is too large, which is often true for high-voltage industrial transient tests, the structures will become permanently damaged and impact device functionality.

Both attenuation and diversion strategies are implemented to protect the internal structures as well as the device itself. Attenuation is realized by capacitor C4 which forms an R/C low-pass filter when interacting with the source impedance of the transient generator, ferrite bead FB1 also helps attenuate high-frequency current, along with both AC and DC current limiters realized by series pass elements R1, R2, and R3. Diversion is achieved by transient voltage suppressor (TVS) diode D7 and clamp-to-rail diodes D5 and D6. The combined effects of both strategies effectively limit the current flowing into the device and through the internal diode structures such that the device is not damaged and remains functional.

It is important to also include TVS diodes D1 and D4 at the VPOS_IN_x and VNEG_IN_x nodes in order to provide a discharge path for the energy that is going to be sent to these nodes through diodes D5, D6, and the internal diode structures. Without these diodes when current is diverted to these nodes the DC/DC converter storage capacitors C1 and C2 will charge, slowly increasing the voltage at these nodes.

9.1.5 Implementing HART with DAC8775

The DAC8775 features internal resistors to convert a 500-mVpp HART FSK signal sourced by an external HART modem. These resistors are ratiometrically matched to the gain-setting resistors for the current output signal chain to ensure that a 500-mVpp input at the HART_IN_x pin is delivered as a 1-mApp signal at the respective IOUT_x pin regardless of which gain mode is selected.

An external capacitor, placed in series between the HART_IN_x pin and HART FSK source, is required to AC couple the HART FSK signal to the HART_IN_x pin. The recommended capacitance for this external capacitor is from 10 nF to 22 nF.

9.2.1 1W Power Dissipation, Quad Channel, EMC and EMI Protected Analog Output Module with Adaptive Power Management

Figure 130. DAC8775 in Quad-Channel PLC AO Module

9.2.2 Design Requirements

Analog I/O modules are used by programmable logic controllers (PLCs) to interface sensors, actuators, and other field instruments. These modules must meet stringent electrical specifications for both accuracy and robust protection. These outputs are typically current outputs based on the 4-mA to 20-mA range and derivatives or voltage outputs ranging from 0 V to 5 V, 0 V to 10 V, ±5 V, and ±10 V. Common error budgets accommodate 0.1% full-scale range total unadjusted error (% FSR TUE) at room temperature. Designs that desire stronger accuracy over temperature frequently implement calibration. Often the PLC back-plane provides access to a 12-V to 36-V analog supply from which a majority of analog supply voltages are derived.

Analog output modules are frequently multi-channel modules featuring either channel-to-channel isolation between each channel or group isolation where several channels share a common ground connection. As channel count increases it is desirable to maintain small form-factor requiring high levels of integration and reduced power dissipation in order to control heat inside of the PLC enclosure.

Therefore the design requirements are:

• Support of standard industrial automation voltage and current output spans
• Operation with standard industrial automation supply voltages from 12 V to 36 V
• Current and voltage outputs with TUE less than 0.1% at 25°C
• Total on-board power dissipation less than or equal to 1 W
• At minimum criteria B IEC61000-4 ESD, EFT, CI, and Surge immunity

9.2.3 Detailed Design Procedure

Figure 131. Generic Design for Typical PLC Current and Voltage Outputs

Figure 131 illustrates a common generic solution for realizing the desired voltage and current output spans for industrial automation applications.

The current output circuit is comprised of amplifiers A1 and A2, MOSFETs Q1 and Q2, and the three resistors RSET, RA, and RB. This two-stage current source enables the ground-referenced DAC output voltage to drive the high-side amplifier required for the current-source.

The voltage output circuit is composed of amplifier A3 and the resistor network consisting of RFB, RG1, and RG2. A3 operates as a modified summing amplifier, where the DAC controls the non-inverting input and inverting input has one path to GND and a second to VREF. This configuration allows the single-ended DAC to create both the unipolar 0-V to 5-V and 0-V to 10-V outputs and the bipolar ±5-V and ±10-V outputs by modifying the values of RG1 and RG2.

Though this generic circuit realizes the desired spans, both the voltage and current outputs have short-comings. The current output high-side supply voltage is typically 24 V, when driving low impedance loads with this supply voltage a considerable amount of power is dissipated on RB and Q2. This power dissipation results in increased heat which leads to drift errors for amplifiers A1 and A2 as well as the DAC, resistors, and the reference voltage. In order to reduce the power dissipation in the high-side voltage to current converter circuit a feedback system which monitors the voltage drop across Q2 and adaptively adjusts the high-side supply voltage can be implemented. This feedback system adjusts the high side supply voltage to the minimum supply required to keep Q2 in the linear region of operation, avoiding compliance voltage saturation, reducing power dissipation and heat to a minimum which helps maintain accuracy.

The generic voltage output circuit performs well but does not compensate for errors associated with excessive output impedance or differences in ground potential from the local PLC ground and the load ground. A modified circuit can be implemented which provides connections to sense errors associated with both output impedance voltage drops and differences in ground potentials, this circuit is shown in Figure 128.

Figure 130 illustrates the DAC8775 along with the LM5166 in a quad-channel PLC analog output module. The DAC8775 includes the generic voltage and current output circuits along with buck-boost converter and feedback circuits for the current output and positive and negative sense connections for the voltage output circuit. The DAC8775 includes an internal reference and internal LDO for supplying the field-side of a digital isolator along with the buck-boost converter generating the single or dual high voltage supplies required for the output circuits, all powered from a single supply.

The DAC8775 buck-boost converter operates at peak efficiency with 12-V input voltage with peak power consumption of approximately 780mW. The LM5166 circuit accepts a wide range of input voltages from just above 12 V to 65 V, providing coverage for most standard PLC supply voltages, and buck-converts this supply voltage to the optimal 12-V supply for the DAC8775. Cumulative power dissipation for the DAC8775 and LM5166 is under 1 W.

Two ISO7641 devices implement galvanic isolation for all of the digital communication lines, though only a single ISO7641 is required for basic communication with the DAC8775 SPI compatible interface. An output protection circuit is included which is designed to provide immunity to the IEC61000-4 industrial transient and radiation test suite. The protection circuit includes transient voltage suppressor (TVS) diodes, clamp-to-rail steering diodes, and pass elements in the form of resistors and ferrite beads.

9.2.4 Application Curves

Figure 132. 4-mA to 20-mA IOUT TUE vs Code

Figure 134. Total On-Board Power Dissipation vs Supply

Figure 133. ±10-V VOUT TUE vs Code

12.1.1 関連資料

関連資料については、以下を参照してください。

• 『DAC8775 EVMユーザー・ガイド』(SBAU248)
• LM5166 3V～65V入力、500mA、超低I_Qの同期整流降圧コンバータ データシート(SNVSA67)
• ISO76x1 低消費電力、トリプルおよびクワッド・チャネルのデジタル・アイソレータ(SLLSEC3)