• Menu
  • Product
  • Email
  • PDF
  • Order now

  • DS90LV028A 3V、LVDSデュアルCMOS差動入力ライン・レシーバ

    • JAJS575F June   1998  – June 2016 DS90LV028A

      PRODUCTION DATA.  

  • CONTENTS
  • SEARCH
  • DS90LV028A 3V、LVDSデュアルCMOS差動入力ライン・レシーバ
  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Fail-Safe Feature
      2. 8.3.2 Cables and Connectors
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Probing LVDS Transmission Lines
        2. 9.2.2.2 Threshold
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Differential Traces
      2. 11.1.2 Termination
    2. 11.2 Layout Examples
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報
  14. 重要なお知らせ

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
  • D|8
    • MSOI002K
  • NGN|8
    • MPDS401A
サーマルパッド・メカニカル・データ
発注情報
  • jajs575f_oa
  • jajs575f_pm
search No matches found.
  • Full reading width
    • Full reading width
    • Comfortable reading width
    • Expanded reading width
  • Card for each section
  • Card with all content

 

DATA SHEET

DS90LV028A 3V、LVDSデュアルCMOS差動入力ライン・レシーバ

このリソースの元の言語は英語です。 翻訳は概要を便宜的に提供するもので、自動化ツール (機械翻訳) を使用していることがあり、TI では翻訳の正確性および妥当性につきましては一切保証いたしません。 実際の設計などの前には、ti.com で必ず最新の英語版をご参照くださいますようお願いいたします。

1 特長

  • 400Mbps (200MHz)を超えるスイッチング速度
  • 差動スキュー: 50ps (標準値)
  • チャネル間スキュー: 0.1ns (標準値)
  • 最大伝搬遅延: 2.5ns
  • 3.3V電源の設計
  • フロースルーのピン配置
  • パワーダウン時高インピーダンスのLVDS入力
  • 低消費電力の設計(3.3V静的で18mW)
  • 既存の5V LVDSネットワークと相互運用可能
  • 小振幅(標準値350mV)差動信号レベルを許容
  • 開放、短絡、終端の入力フェイルセーフに対応
  • ANSI/TIA/EIA-644規格に準拠
  • 工業用温度範囲: -40℃～85℃
  • SOICおよび省スペースのWSONパッケージで供給

2 アプリケーション

  • 多機能プリンタ
  • LVDS-LVCMOS間の変換
  • ビル・オートメーションとファクトリ・オートメーション
  • グリッド・インフラストラクチャ

3 概要

DS90LV028AはデュアルCMOS差動ライン・レシーバで、超低消費電力、低ノイズ、高いデータ速度を必要とするアプリケーション用に設計されています。このデバイスは、低電圧差動信号(LVDS)テクノロジを活用し、400Mbps (200MHz)を超えるデータ速度をサポートするよう設計されています。

DS90LV028Aは低電圧(標準値350mV)の差動入力信号を受信し、3V CMOS出力レベルへ変換します。また、レシーバは開放、短絡、終端(100Ω)の入力フェイルセーフもサポートします。すべてのフェイルセーフ条件において、レシーバの出力はHIGHになります。DS90LV028Aにはフロースルー設計が採用されているため、PCBレイアウトが容易です。

DS90LV028Aと、対になるLVDSライン・ドライバは、消費電力の大きいPECL/ECLデバイスの代替として、高速のポイント・ツー・ポイント・インターフェイス・アプリケーションに使用できます。

製品情報(1)

型番 パッケージ 本体サイズ(公称)
DS90LV028A SOIC (8) 4.90mm×3.91mm
WSON (8) 4.00mm×4.00mm
  1. 提供されているすべてのパッケージについては、巻末の注文情報を参照してください。

機能図

DS90LV028A 10007702.gif

4 改訂履歴

Changes from E Revision (April 2013) to F Revision

  • 「ESD定格」の表、「機能説明」セクション、「デバイスの機能モード」セクション、「アプリケーションと実装」セクション、「電源に関する推奨事項」セクション、「レイアウト」セクション、「デバイスおよびドキュメントのサポート」セクション、「メカニカル、パッケージ、および注文情報」セクションを追加Go
  • Added Thermal Information valuesGo

Changes from D Revision (April 2013) to E Revision

  • Changed ナショナル・セミコンダクターのデータシートのレイアウトをTIフォーマットへGo

5 Pin Configuration and Functions

D Package
8-Pin SOIC
Top View
DS90LV028A 10007701.png
NGN Package
8-Pin WSON
Top View
DS90LV028A 10007725.png

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
GND 5 — Ground pin
RIN+ 2, 3 I Noninverting receiver input pin
RIN– 1, 4 I Inverting receiver input pin
ROUT 6, 7 O Receiver output pin
VCC 8 — Power supply pin, 3.3 V ±0.3 V

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage, VCC –0.3 4 V
Input voltage, RIN+, RIN− –0.3 3.9 V
Output voltage, ROUT –0.3 VCC + 0.3 V
Maximum package power dissipation at 25°C D package 1025 mW
Derate D package 8.2 mW/°C
above 25°C		 °C
NGN package 3.3 W
Derate NGN package 25.6 mW/°C
above 25°C		 °C
Lead temperature range, soldering (4 s) 260 °C
Junction temperature, TJ 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±7000 V
Machine model (MM)(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) EIAJ, 0 Ω, 200 pF

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC Supply voltage 3 3.3 3.6 V
Receiver input voltage GND 3 V
TA Operating free-air temperature –40 25 85 °C

6.4 Thermal Information

THERMAL METRIC(1) DS90LV028A UNIT
D (SOIC) NGN (WSON)
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance — 35.9 °C/W
Low-K thermal resistance 212 —
High-K thermal resistance 122 —
RθJC(top) Junction-to-case (top) thermal resistance 69.1 24.2 °C/W
RθJB Junction-to-board thermal resistance 47.7 13.2 °C/W
ψJT Junction-to-top characterization parameter 15.2 0.2 °C/W
ψJB Junction-to-board characterization parameter 47.2 13.3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — 2.9 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN TYP(2) MAX UNIT
VTH Differential input high threshold VCM = 1.2 V, 0 V, 3 V, RIN+, RIN− pins(3) 100 mV
VTL Differential input low threshold VCM = 1.2 V, 0 V, 3 V, RIN+, RIN− pins(3) –100 mV
IIN Input current VCC = 3.6 V or 0 V,
RIN+, RIN− pins		 VIN = 2.8 V –10 ±1 10 μA
VIN = 0 V –10 ±1 10
VCC = 0 V, VIN = 3.6 V, RIN+, RIN− pins –20 20
VOH Output high voltage IOH = –0.4 mA, VID = 200 mV, ROUT pin 2.7 3.1 V
IOH = –0.4 mA, inputs terminated, ROUT pin 2.7 3.1
IOH = –0.4 mA, inputs shorted, ROUT pin 2.7 3.1
VOL Output low voltage IOL = 2 mA, VID = –200 mV, ROUT pin 0.3 0.5 V
IOS Output short-circuit current VOUT = 0 V, ROUT pin(4) –15 –50 –100 mA
VCL Input clamp voltage ICL = –18 mA, ROUT pin –1.5 –0.8 V
ICC No load supply current VCC pin, inputs open 5.4 9 mA
(1) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground unless otherwise specified (such as VID).
(2) All typicals are given for: VCC = 3.3 V and TA = 25°C.
(3) VCC is always higher than RIN+ and RIN− voltage. RIN+ and RIN− are allowed to have voltage range –0.05 V to 3.05 V. VID is not allowed to be greater than 100 mV when VCM = 0 V or 3 V.
(4) Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output must be shorted at a time, do not exceed maximum junction temperature specification.

6.6 Switching Characteristics

VCC = 3.3 V ±10%, and TA = −40°C to 85°C (unless otherwise noted)(1)(2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPHLD Differential propagation delay high to low CL = 15 pF 1 1.6 2.5 ns
tPLHD Differential propagation delay low to high VID = 200 mV 1 1.7 2.5 ns
tSKD1 Differential pulse skew |tPHLD − tPLHD|(3) See Figure 18 and Figure 19 0 50 400 ps
tSKD2 Differential channel-to-channel skew-same device(4) 0 0.1 0.5 ns
tSKD3 Differential part to part skew(5) 0 1 ns
tSKD4 Differential part to part skew(6) 0 1.5 ns
tTLH Rise Time 325 800 ps
tTHL Fall Time 225 800 ps
fMAX Maximum operating frequency(7) 200 250 MHz
(1) CL includes probe and jig capacitance.
(2) Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50 Ω, tr and tf (0% to 100%) ≤ 3 ns for RIN.
(3) tSKD1 is the magnitude difference in differential propagation delay time between the positive-going-edge and the negative-going-edge of the same channel.
(4) tSKD2 is the differential channel-to-channel skew of any event on the same device. This specification applies to devices having multiple receivers within the integrated circuit.
(5) tSKD3, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range.
(6) tSKD4, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over the recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Maximum − Minimum| differential propagation delay.
(7) fMAX generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, differential (1.05V to 1.35 peak to peak). Output criteria: 60%/40% duty cycle, VOL (max 0.4V), VOH (min 2.7V), load = 15 pF (stray plus probes).

6.7 Typical Characteristics

DS90LV028A 10007707.png Figure 1. Output High Voltage
vs Power Supply Voltage
DS90LV028A 10007709.png Figure 3. Output Short Circuit Current
vs Power Supply Voltage
DS90LV028A 10007712.png Figure 5. Power Supply Current
vs Ambient Temperature
DS90LV028A 10007714.png Figure 7. Differential Propagation Delay
vs Ambient Temperature
DS90LV028A 10007716.png Figure 9. Differential Skew
vs Ambient Temperature
DS90LV028A 10007717.png Figure 11. Differential Propagation Delay
vs Differential Input Voltage
DS90LV028A 10007720.png Figure 13. Transition Time
vs Ambient Temperature
DS90LV028A 10007722.png Figure 15. Transition Time
vs Load
DS90LV028A 10007724.png Figure 17. Transition Time
vs Load
DS90LV028A 10007708.png Figure 2. Output Low Voltage
vs Power Supply Voltage
DS90LV028A 10007710.png Figure 4. Differential Transition Voltage
vs Power Supply Voltage
DS90LV028A 10007713.png Figure 6. Differential Propagation Delay
vs Power Supply Voltage
DS90LV028A 10007715.png Figure 8. Differential Skew
vs Power Supply Voltage
DS90LV028A 10007718.png Figure 10. Differential Propagation Delay
vs Common Mode Voltage
DS90LV028A 10007719.png Figure 12. Transition Time
vs Power Supply Voltage
DS90LV028A 10007721.png Figure 14. Differential Propagation Delay
vs Load
DS90LV028A 10007723.png Figure 16. Differential Propagation Delay
vs Load

 
Texas Instruments

© Copyright 1995-2025 Texas Instruments Incorporated. All rights reserved.
Submit documentation feedback | IMPORTANT NOTICE | Trademarks | Privacy policy | Cookie policy | Terms of use | Terms of sale